http://www.freshpatents.com/Active-solid-state-devices--e-g--transistors-solid-state-diodes--dtnewntc257.php USPTO Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes) en-us Mon, 20 May 2013 13:35:02 -0700 1000 Wednesday Thursday Friday Saturday Sunday 141 31 http://www.freshpatents.com/index.php?rss=true http://www.freshpatents.com/images/freshpatentsnav_rss.gif http://www.freshpatents.com/-dt20130516ptan20130119336.php Mon, 20 May 2013 13:35:02 -0700 Non-volatile memory devices with two stacked layers of chalcogenide materials comprising the active memory device have been investigated for their potential as phase-change memories. The devices tested included GeTe/SnTe, Ge2Se3/SnTe, and Ge2Se3/SnSe stacks. All devices exhibited resistance switching behavior. The polarity of the applied voltage with respect to the SnTe... http://www.freshpatents.com/-dt20130516ptan20130119339.php Mon, 20 May 2013 13:35:02 -0700 A phase change memory cell with substantially void free crystalline phase change material. An example memory cell includes a substrate and a bottom electrode carried by the substrate. The bottom electrode is a thermal conductor. A phase change layer includes phase change material. The phase change layer is void free... http://www.freshpatents.com/-dt20130516ptan20130119338.php Mon, 20 May 2013 13:35:02 -0700 A memory cell is provided that includes a diode and a resistance-switching material layer coupled in series with the diode. The resistance-switching material layer: (a) includes a material from the family consisting of XvOw, wherein X represents an element from the family consisting of Hf and Zr, and wherein the... http://www.freshpatents.com/-dt20130516ptan20130119337.php Mon, 20 May 2013 13:35:02 -0700 A resistive-switching random access memory device includes a memory cell disposed between a bit line and a word line, the memory cell having a resistive-switching element (40) and a Schottky diode (30). The Schottky diode (30) and the resistive-switching element (40) are connected in series. The Schottky diode (30) includes... http://www.freshpatents.com/-dt20130516ptan20130119342.php Mon, 20 May 2013 13:35:02 -0700 According to one embodiment, a method is disclosed for manufacturing a semiconductor memory device. The method can include introducing halogen in a contact layer with a resistance variation film including a metal oxide. The method can include diffusing the halogen from the contact layer to the resistance variation film by... http://www.freshpatents.com/-dt20130516ptan20130119340.php Mon, 20 May 2013 13:35:02 -0700 This invention proposes a multi-bit resistive-switching memory cell and array thereof. Multiple conduction paths are formed on each memory cell and independent of each other, and each conduction path can be in a high-resistance or low-resistance state, so as to form a multi-bit resistive-switching memory cell. A memory cell array... http://www.freshpatents.com/-dt20130516ptan20130119344.php Mon, 20 May 2013 13:35:02 -0700 A variable resistance nonvolatile storage element includes: a first electrode; a second electrode; and a variable resistance layer having a resistance value that reversibly changes based on an electrical signal applied between the electrodes, wherein the variable resistance layer has a structure formed by stacking a first transition metal oxide... http://www.freshpatents.com/-dt20130516ptan20130119343.php Mon, 20 May 2013 13:35:02 -0700 A resistive random access memory and a method for fabricating the same are provided. The method includes forming a bottom electrode on a substrate; forming a metal oxide layer on the bottom electrode; forming an oxygen atom gettering layer on the metal oxide layer; forming a first top electrode sub-layer... http://www.freshpatents.com/-dt20130516ptan20130119341.php Mon, 20 May 2013 13:35:02 -0700 A Resistive Random Access Memory (RRAM) cell and a memory are disclosed. In one embodiment, the RRAM cell comprises a two-state resistor and a resistive switching memory cell connected in series. The two-state resistor can supply relatively large currents under both positive and negative voltage polarities. As a result, it... http://www.freshpatents.com/-dt20130516ptan20130119345.php Mon, 20 May 2013 13:35:02 -0700 A thin film transistor includes a gate electrode configured to receive a control voltage, a source electrode insulated from the gate electrode, and configured to receive an input voltage, a drain electrode insulated from the gate electrode, and configured to receive an output voltage, at least two carbon nanotube patterns... http://www.freshpatents.com/-dt20130516ptan20130119346.php Mon, 20 May 2013 13:35:02 -0700 An apparatus includes a nanocrystal. The nanocrystal includes a core including FeS2; and a coating including a ligand component capable of chemically interacting with both an iron atom and a sulfur atom on a surface of the core.... http://www.freshpatents.com/-dt20130516ptan20130119347.php Mon, 20 May 2013 13:35:02 -0700 A semiconductor device including a group III-V barrier and a method of manufacturing the semiconductor device, the semiconductor device including: a substrate, insulation layers formed to be spaced apart on the substrate, a group III-V material layer for filling the space between the insulation layers and having a portion protruding... http://www.freshpatents.com/-dt20130516ptan20130119349.php Mon, 20 May 2013 13:35:02 -0700 A graphene transistor includes: a gate electrode on a substrate; a gate insulating layer on the gate electrode; a graphene channel on the gate insulating layer; a source electrode and a drain electrode on the graphene channel, the source and drain electrode being separate from each other; and a cover... http://www.freshpatents.com/-dt20130516ptan20130119348.php Mon, 20 May 2013 13:35:02 -0700 RF transistors are fabricated at complete wafer scale using a nanotube deposition technique capable of forming high-density, uniform semiconducting nanotube thin films at complete wafer scale, and electrical characterization reveals that such devices exhibit gigahertz operation, linearity, and large transconductance and current drive.... http://www.freshpatents.com/-dt20130516ptan20130119350.php Mon, 20 May 2013 13:35:02 -0700 A semiconductor structure including an ordered array of parallel graphene nanoribbons located on a surface of a semiconductor substrate is provided using a deterministically assembled parallel set of nanowires as an etch mask. The deterministically assembled parallel set of nanowires is formed across a gap present in a patterned graphene... http://www.freshpatents.com/-dt20130516ptan20130119351.php Mon, 20 May 2013 13:35:02 -0700 Methods are provided of forming a Josephson junction (JJ) quantum bit (qubit). In one embodiment, the method comprises forming a JJ trilayer on a substrate. The JJ trilayer is comprised of a dielectric layer sandwiched between a bottom superconductor material layer and a top superconductor material layer. The method further... http://www.freshpatents.com/-dt20130516ptan20130119365.php Mon, 20 May 2013 13:35:02 -0700 An object of the present invention is to provide a composite material formed of an organic compound and an inorganic compound, and has an excellent carrier transporting property, an excellent carrier injecting property to the organic compound, as well as excellent transparency. A composite material of the present invention for... http://www.freshpatents.com/-dt20130516ptan20130119364.php Mon, 20 May 2013 13:35:02 -0700 A light-emitting device includes a transistor over a substrate and an insulating film over the transistor. The light-emitting device further includes a wiring over the insulating film and a light-emitting element. The insulating film includes a first opening and a second opening, and the wiring is electrically connected to the... http://www.freshpatents.com/-dt20130516ptan20130119363.php Mon, 20 May 2013 13:35:02 -0700 A fluorine-containing aromatic compound represented by a formula: Q(W—ArF(Z)k)n is provided. The Q is an n-valent aromatic hydrocarbon group obtained by removing n-pieces of hydrogen atoms from a monocyclic structure, a polycyclic assembly structure, or a condensed polycyclic structure of one or more benzene rings or heterocycles. The W is... http://www.freshpatents.com/-dt20130516ptan20130119354.php Mon, 20 May 2013 13:35:02 -0700 Novel phosphorescent heteroleptic iridium complexes with phenylpyridine and dibenzo-containing ligands are provided. The disclosed compounds have low sublimation temperatures that allow for ease of purification and fabrication into a variety of OLED devices.... http://www.freshpatents.com/-dt20130516ptan20130119367.php Mon, 20 May 2013 13:35:02 -0700 The present invention relates to a highly efficient carbazole-based compound and to an organic electroluminescence device including the same. According to the present invention, provided are a compound for an organic electroluminescence device and an organic electroluminescence device including the compound, in which a carbazole-based phosphine oxide compound, which is... http://www.freshpatents.com/-dt20130516ptan20130119369.php Mon, 20 May 2013 13:35:02 -0700 and a method for manufacturing the aromatic compound having, on a hydrocarbon side chain, at least one type of group having a cationic center, the method comprising reacting the aromatic compound having a leaving group on a hydrocarbon side chain with a specific nitrogen compound, phosphorus compound, sulfur compound, or... http://www.freshpatents.com/-dt20130516ptan20130119358.php Mon, 20 May 2013 13:35:02 -0700 Provided is a light-emitting device having a light-emitting portion having a light-emitting element in a space surrounded by a support substrate, a metal substrate, and a sealing material, in which the sealing material is provided to surround the periphery of the light-emitting portion, the light-emitting element has a first electrode,... http://www.freshpatents.com/-dt20130516ptan20130119352.php Mon, 20 May 2013 13:35:02 -0700 Described is a method for making a flexible OLED lighting device. The method includes forming a plurality of OLED elements on a flexible planar substrate, each of the OLED elements including a continuous respective anode layer formed over the substrate. One or more organic light emitting materials is formed over... http://www.freshpatents.com/-dt20130516ptan20130119356.php Mon, 20 May 2013 13:35:02 -0700 Opal glass compositions and devices incorporating opal glass compositions are described herein. The compositions solve problems associated with the use of opal glasses as light-scattering layers in electroluminescent devices, such as organic light-emitting diodes. In particular, embodiments solve the problem of high light absorption within the opal glass layer as... http://www.freshpatents.com/-dt20130516ptan20130119368.php Mon, 20 May 2013 13:35:02 -0700 An organic EL device includes a first substrate having electrical conductivity, an organic layer formed on the first substrate, an electrode layer formed on the organic layer, and a second substrate joined to the electrode layer by an adhesive layer. In a region of a peripheral portion of the first... http://www.freshpatents.com/-dt20130516ptan20130119366.php Mon, 20 May 2013 13:35:02 -0700 The present invention aims to provide organic EL elements operating at low voltage to emit light at high intensity. For this aim, each EL element includes an anode, a cathode, a functional layer disposed between the anode and the cathode and including a light-emitting layer composed of organic material, a... http://www.freshpatents.com/-dt20130516ptan20130119360.php Mon, 20 May 2013 13:35:02 -0700 wherein, X represents O or S; Y1 to Y3 each represents a hydrogen atom, a substituent or a group represented by Formula (A) disclosed un the specification, provided that at least two of Y1 to Y3 are groups represented by Formula (A), not all of Y1 to Y3 are the... http://www.freshpatents.com/-dt20130516ptan20130119359.php Mon, 20 May 2013 13:35:02 -0700 where R1 to R12 each independently represents a hydrogen atom or a substituent and which may be bound to each other to form a non-aromatic ring, where Z1 to Z4 each independently represents a hydrogen atom or a substituent, and where Z1 and Z2, and Z3 and Z4 may be... http://www.freshpatents.com/-dt20130516ptan20130119362.php Mon, 20 May 2013 13:35:02 -0700 An organic light emitting diode (OLED) display. The OLED display includes a first substrate member, a first conductive wire having a contact region and formed over the first substrate member, an insulating layer including a plurality of wire contact holes exposing a part of the contact region of the first... http://www.freshpatents.com/-dt20130516ptan20130119361.php Mon, 20 May 2013 13:35:02 -0700 wherein at least one of R8 to R14 is phenyl or substituted phenyl, and/or at least two of R8 to R14 that are adjacent are part of a fluorenyl group. The emissive materials have enhanced electroluminescent efficiency and improved lifetime when incorporated into light emitting devices. The invention provides emissive materials... http://www.freshpatents.com/-dt20130516ptan20130119355.php Mon, 20 May 2013 13:35:02 -0700 The styryl-based compound may exhibit high heat resistance and thus an OLED including the same may have low driving voltage, high brightness, high efficiency, and long lifetime. A styryl-based compound represented by Formula 1, a composition containing the styryl-based compound, and an organic light-emitting diode (OLED) including the styryl-based compound:... http://www.freshpatents.com/-dt20130516ptan20130119353.php Mon, 20 May 2013 13:35:02 -0700 Novel aryl silicon and aryl germanium host materials, and in particular host materials containing triphenylene and pyrene fragments, are described. These compounds improve OLED device performance when used as hosts in the emissive layer of the OLED.... http://www.freshpatents.com/-dt20130516ptan20130119357.php Mon, 20 May 2013 13:35:02 -0700 with respect to emissions of the first and second stacks, where λ is an emission peak wavelength of the first stack or the second stack, na and da are a refractive index and a thickness of a transparent electrode selected from the first and second electrode, and nw and dw... http://www.freshpatents.com/-dt20130516ptan20130119371.php Mon, 20 May 2013 13:35:02 -0700 An active device including a source, a drain, an oxide semiconductor layer, a gate and a gate insulator layer is provided. The source includes first stripe electrodes parallel to each other and a first connection electrode connected thereto. The drain includes second stripe electrodes parallel to each other and a... http://www.freshpatents.com/-dt20130516ptan20130119379.php Mon, 20 May 2013 13:35:02 -0700 It is an object of the present invention to provide a light-emitting device in which, even when a material with high reflectivity such as aluminum is used for an electrode, a layer containing oxygen can be formed over the electrode without increasing contact resistance and a manufacturing method thereof. According... http://www.freshpatents.com/-dt20130516ptan20130119372.php Mon, 20 May 2013 13:35:02 -0700 A light sensing device is disclosed. The light sensing device includes a first light sensor and a second light sensor. The first light sensor formed on a substrate includes a first metal oxide semiconductor layer for absorbing a first light having a first waveband. The second light sensor formed on... http://www.freshpatents.com/-dt20130516ptan20130119374.php Mon, 20 May 2013 13:35:02 -0700 To provide a photoelectric conversion device which has little light loss caused by light absorption in a window layer and has favorable electric characteristics. The photoelectric conversion device includes, between a pair of electrodes, a light-transmitting semiconductor layer which has one conductivity type and serves as a window layer, and... http://www.freshpatents.com/-dt20130516ptan20130119373.php Mon, 20 May 2013 13:35:02 -0700 A highly reliable semiconductor device is provided. Over an oxide semiconductor layer in which a channel is formed, an insulating layer including the oxide semiconductor material having a higher insulating property than an oxide semiconductor layer is formed. A material which contains an element M and is represented by a... http://www.freshpatents.com/-dt20130516ptan20130119378.php Mon, 20 May 2013 13:35:02 -0700 The semiconductor device includes a power element which is in an on state when voltage is not applied to a gate, a switching field-effect transistor for applying first voltage to the gate of the power element, and a switching field-effect transistor for applying voltage lower than the first voltage to... http://www.freshpatents.com/-dt20130516ptan20130119380.php Mon, 20 May 2013 13:35:02 -0700 A solid-state image sensor which holds a potential for a long time and includes a thin film transistor with stable electrical characteristics is provided. When the off-state current of a thin film transistor including an oxide semiconductor layer is set to 1×10−13 A or less and the thin film transistor... http://www.freshpatents.com/-dt20130516ptan20130119376.php Mon, 20 May 2013 13:35:02 -0700 To provide a highly reliable semiconductor device including a transistor using an oxide semiconductor. After a source electrode layer and a drain electrode layer are formed, an island-like oxide semiconductor layer is formed in a gap between these electrode layers so that a side surface of the oxide semiconductor layer... http://www.freshpatents.com/-dt20130516ptan20130119375.php Mon, 20 May 2013 13:35:02 -0700 Provided is a miniaturized transistor having high electrical characteristics. The transistor includes a source electrode layer in contact with one side surface of the oxide semiconductor layer in the channel-length direction and a drain electrode layer in contact with the other side surface thereof. The transistor further includes a gate... http://www.freshpatents.com/-dt20130516ptan20130119377.php Mon, 20 May 2013 13:35:02 -0700 By reducing the contact resistance between an oxide semiconductor film and a metal film, a transistor that uses an oxide semiconductor film and has excellent on-state characteristics is provided. A semiconductor device includes a pair of electrodes over an insulating surface; an oxide semiconductor film in contact with the pair... http://www.freshpatents.com/-dt20130516ptan20130119370.php Mon, 20 May 2013 13:35:02 -0700 A strained structure of a semiconductor device is disclosed. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a gate stack on the major surface of the substrate; a shallow trench isolation (STI) disposed on one side of the gate stack, wherein the STI is... http://www.freshpatents.com/-dt20130516ptan20130119381.php Mon, 20 May 2013 13:35:02 -0700 The present invention provides a zinc oxide-based ultraviolet light emitting material showing intense emission in the ultraviolet region. The present invention is an ultraviolet light emitting material containing: zinc and oxygen as main components; at least one element selected from the group consisting of aluminum, gallium, and indium, as a... http://www.freshpatents.com/-dt20130516ptan20130119382.php Mon, 20 May 2013 13:35:02 -0700 A system and method for plating a contact is provided. An embodiment comprises forming protective layers over a contact and a test pad, and then selectively removing the protective layer over the contact without removing the protective layer over the test pad. With the protective layer still on the test... http://www.freshpatents.com/-dt20130516ptan20130119384.php Mon, 20 May 2013 13:35:02 -0700 A parasitic lateral PNP transistor is disclosed, in which, an N-type implanted region formed in each of two adjacent active regions forms a base region; a P-type doped polysilicon pseudo buried layer located under a shallow trench field oxide region between the two active regions serves as an emitter; and... http://www.freshpatents.com/-dt20130516ptan20130119383.php Mon, 20 May 2013 13:35:02 -0700 Thin-film transistors and techniques for forming thin-film transistors (TFT). In some embodiments, there is provided a method of forming a TFT, comprising forming a body region of the TFT comprising an organic semiconducting material, and forming a protective layer comprising an organic insulating material. Forming the protective layer comprises contacting... http://www.freshpatents.com/-dt20130516ptan20130119385.php Mon, 20 May 2013 13:35:02 -0700 A pixel structure includes a substrate; a scan line; a gate electrode; an insulating layer disposed on the scan line, the gate electrode and the substrate; a channel and a data line disposed on the insulating layer; a source electrode and a drain electrode disposed on the channel; a passivation... http://www.freshpatents.com/-dt20130516ptan20130119387.php Mon, 20 May 2013 13:35:02 -0700 An organic light-emitting display apparatus includes: a substrate including an emission region and a non-emission region and having a recess formed in at least a portion of the non-emission region; a black matrix disposed in the recess; a thin film transistor disposed on the non-emission region of the substrate and... http://www.freshpatents.com/-dt20130516ptan20130119388.php Mon, 20 May 2013 13:35:02 -0700 An OLED device includes: a TFT including an active layer, gate, source and drain electrodes, a first insulating layer between the active layer and the gate electrode, and a second insulating layer between the source and drain electrodes, a pixel electrode on the first and second insulating layers, connected to... http://www.freshpatents.com/-dt20130516ptan20130119386.php Mon, 20 May 2013 13:35:02 -0700 A pixel structure and its fabrication method are provided. The pixel structure includes a channel layer, a first patterned metal layer, a first insulation layer, a second patterned metal layer, a second insulation layer, and a pixel electrode. The first patterned metal layer includes a data line, a source, and... http://www.freshpatents.com/-dt20130516ptan20130119389.php Mon, 20 May 2013 13:35:02 -0700 A FET is formed on a semiconductor substrate, a curved surface having a radius of curvature is formed on an upper end of an insulation, a portion of a first electrode is exposed corresponding to the curved surface to form an inclined surface, and a region defining a luminescent region... http://www.freshpatents.com/-dt20130516ptan20130119390.php Mon, 20 May 2013 13:35:02 -0700 A thin film transistor substrate including a thin film transistor having a drain electrode with an electrode portion, which overlaps with a semiconductor layer, and an extended portion, which extends from the electrode portion and has a portion overlapping with a storage electrode or storage electrode line. A passivation layer... http://www.freshpatents.com/-dt20130516ptan20130119391.php Mon, 20 May 2013 13:35:02 -0700 A thin-film transistor device includes: a gate electrode above a substrate; a gate insulating film on the gate electrode; a crystalline silicon thin film including a channel region which is provided on the gate insulating film; semiconductor films on at least the channel region; an insulating film made of an... http://www.freshpatents.com/-dt20130516ptan20130119392.php Mon, 20 May 2013 13:35:02 -0700 An organic light-emitting display device having a thin film transistor including an active layer, a gate electrode, a lower gate electrode, an upper gate electrode, an insulating layer covering the gate electrode, source and drain electrodes that are formed on the insulating layer and contact the active layer. An organic... http://www.freshpatents.com/-dt20130516ptan20130119404.php Mon, 20 May 2013 13:35:02 -0700 Methods and apparatuses for forming a device structure including a high-thermal-conductivity substrate are disclosed herein. A method forming such a device structure may comprise forming an active layer over a first substrate in a manner such that a frontside of the active layer faces the first substrate and a backside... http://www.freshpatents.com/-dt20130516ptan20130119401.php Mon, 20 May 2013 13:35:02 -0700 Techniques for processing materials in supercritical fluids including processing in a capsule disposed within a high-pressure apparatus enclosure are disclosed. The disclosed techniques are useful for growing crystals of GaN, AlN, InN, and their alloys, including InGaN, AlGaN, and AlInGaN for the manufacture of bulk or patterned substrates, which in... http://www.freshpatents.com/-dt20130516ptan20130119402.php Mon, 20 May 2013 13:35:02 -0700 Disclosed is a method for fabricating a light emitting device. The method includes forming an oxide including gallium aluminum over a gallium oxide substrate, forming a nitride including gallium aluminum over the oxide including gallium aluminum and forming a light emitting structure over the nitride including gallium aluminum.... http://www.freshpatents.com/-dt20130516ptan20130119399.php Mon, 20 May 2013 13:35:02 -0700 The present invention discloses a new testing method of group III-nitride wafers. By utilizing the ammonothermal method, GaN or other Group III-nitride wafers can be obtained by slicing the bulk GaN ingots. Since these wafers originate from the same ingot, these wafers have similar properties/qualities. Therefore, properties of wafers sliced... http://www.freshpatents.com/-dt20130516ptan20130119397.php Mon, 20 May 2013 13:35:02 -0700 Disclosed is a semiconductor device. More specifically, disclosed are a nitride-based heterojunction semiconductor device and a method for manufacturing the same. The nitride-based heterojunction semiconductor device includes a first drain electrode, a conductive semiconductor layer including a nitride-based semiconductor disposed on the first drain electrode, a channel layer disposed on... http://www.freshpatents.com/-dt20130516ptan20130119398.php Mon, 20 May 2013 13:35:02 -0700 A nitride-based semiconductor light-emitting device 100 includes a GaN substrate 10, of which the principal surface is an m-plane 12, a semiconductor multilayer structure 20 that has been formed on the m-plane 12 of the GaN-based substrate 10, and an electrode 30 arranged on the semiconductor multilayer structure 20. The... http://www.freshpatents.com/-dt20130516ptan20130119400.php Mon, 20 May 2013 13:35:02 -0700 A method of fabricating a GaN HEMT includes growing a first epitaxial layer on a substrate, growing a second epitaxial layer on the first epitaxial layer, growing a third epitaxial layer on the second epitaxial layer, depositing a first dielectric film on the third epitaxial layer, using dielectric films to... http://www.freshpatents.com/-dt20130516ptan20130119403.php Mon, 20 May 2013 13:35:02 -0700 Some embodiments show a semiconductor structure including a substrate with a {100} crystal surface plane which includes a plurality of adjacent structured regions at a top side of the substrate. The plurality of adjacent structured regions includes adjacent substrate surfaces with {111} crystal planes and a III-V semiconductor material layer... http://www.freshpatents.com/-dt20130516ptan20130119394.php Mon, 20 May 2013 13:35:02 -0700 A termination structure for a nitride-based Schottky diode includes a guard ring formed by an epitaxially grown P-type nitride-based compound semiconductor layer and dielectric field plates formed on the guard ring. The termination structure is formed at the edge of the anode electrode of the Schottky diode and has the... http://www.freshpatents.com/-dt20130516ptan20130119395.php Mon, 20 May 2013 13:35:02 -0700 A tunnel field-effect transistor (TFET) includes a gate electrode, a source region, and a drain region. The source and drain regions are of opposite conductivity types. A channel region is disposed between the source region and the drain region. A source diffusion barrier is disposed between the channel region and... http://www.freshpatents.com/-dt20130516ptan20130119396.php Mon, 20 May 2013 13:35:02 -0700 Two-terminal switching devices characterized by high on/off current ratios and by high breakdown voltage are provided. These devices can be employed as switches in the driving circuits of active matrix displays, e.g., in electrophoretic, rotating element and liquid crystal displays. The switching devices include two electrodes, and a layer of... http://www.freshpatents.com/-dt20130516ptan20130119393.php Mon, 20 May 2013 13:35:02 -0700 A vertical conduction nitride-based Schottky diode is formed using an insulating substrate which was lifted off after the diode device is encapsulated on the front side with a wafer level molding compound. The wafer level molding compound provides structural support on the front side of the diode device to allow... http://www.freshpatents.com/-dt20130516ptan20130119407.php Mon, 20 May 2013 13:35:02 -0700 A method for manufacturing a semiconductor device includes the steps of: preparing a substrate made of silicon carbide; forming, in the substrate, a trench opened on one main surface side of the substrate; and forming an oxide film in a region including a surface of the trench. In the step... http://www.freshpatents.com/-dt20130516ptan20130119405.php Mon, 20 May 2013 13:35:02 -0700 The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate. The semiconductor device includes a gate that is disposed over the substrate. The substrate has a recess. The semiconductor device includes a trench liner that is coated along the recess. The trench liner contains a semiconductor... http://www.freshpatents.com/-dt20130516ptan20130119406.php Mon, 20 May 2013 13:35:02 -0700 A silicon carbide substrate includes a base layer made of silicon carbide, silicon carbide layers made of single-crystal silicon carbide and arranged side by side on the base layer when viewed in plan view, and a filling portion made of silicon carbide and filling a gap formed between the adjacent... http://www.freshpatents.com/-dt20130516ptan20130119408.php Mon, 20 May 2013 13:35:02 -0700 An inexpensive display device, as well as an electrical apparatus employing the same, can be provided. In the display device in which a pixel section and a driver circuit are included on one and the same insulating surface, the driver circuit includes a decoder 100 and a buffer section 101.... http://www.freshpatents.com/-dt20130516ptan20130119409.php Mon, 20 May 2013 13:35:02 -0700 A semiconductor DC transformer is provided. The semiconductor DC transformer comprises: a plurality of semiconductor electricity-to-light conversion structures connected in series for converting input electric energy into optical energy; and a plurality of semiconductor light-to-electricity conversion structures connected in series for converting input optical energy into electric energy, in which... http://www.freshpatents.com/-dt20130516ptan20130119411.php Mon, 20 May 2013 13:35:02 -0700 A light emitting diode package structure includes a substrate, LED bare chips and a lens. The substrate has an upper surface, a lower surface and a side surface between the upper surface and the lower surface. The upper surface is provided with a circuit pattern. The side surface is provided... http://www.freshpatents.com/-dt20130516ptan20130119414.php Mon, 20 May 2013 13:35:02 -0700 A light-emitting device comprises a lattice structure to minimize the horizontal waveguide effect by reducing light traveling distance in the light-absorption medium of the light-emitting devices, and to enhance light extraction from the light-emitting layer. The lattice structure includes sidewalls and/or rods embedded in the light-absorption medium and dividing the... http://www.freshpatents.com/-dt20130516ptan20130119413.php Mon, 20 May 2013 13:35:02 -0700 A light-emitter including: a transparent first electrode; a charge injection transport layer; a light-emitting layer; and a transparent second electrode, layered in this order. The light-emitting layer is defined by a bank. The charge injection transport layer has a recessed structure including: an inner bottom surface in contact with a... http://www.freshpatents.com/-dt20130516ptan20130119412.php Mon, 20 May 2013 13:35:02 -0700 An electro-optical device formed on a semiconductor substrate, includes: a first transistor controlling a current level according to a voltage between a gate and a source; a second transistor electrically connected between a data line and the gate of the first transistor; a third transistor electrically connected between the gate... http://www.freshpatents.com/-dt20130516ptan20130119410.php Mon, 20 May 2013 13:35:02 -0700 A white LED lighting device driven by a pulse current is provided, which consists of blue, violet or ultraviolet LED chips, blue afterglow luminescence materials A and yellow luminescence materials B. Wherein the weight ratio of the blue afterglow luminescence materials A to the yellow luminescence materials B is 10-70... http://www.freshpatents.com/-dt20130516ptan20130119415.php Mon, 20 May 2013 13:35:02 -0700 An LED package structure for enhancing mixed light effect comprises: at least one first light emitting chip; at least one second light emitting chip, a frame structure having a first containing portion, a second containing portion, a spacing portion and a light mixing area; a first colloid, doped with a... http://www.freshpatents.com/-dt20130516ptan20130119416.php Mon, 20 May 2013 13:35:02 -0700 To provide a light-emitting diode enabling improvements to color purity as well as to luminous efficiency, a light-emitting diode comprises a reflective electrode and a transparent electrode having functional layers therebetween, the functional layers being a transparent conductive layer, a hole injection layer, and a hole transport layer, and further... http://www.freshpatents.com/-dt20130516ptan20130119417.php Mon, 20 May 2013 13:35:02 -0700 Light emitting diode (LED) packages and methods are disclosed herein. In one aspect, a light emitting package is disclosed. The light emitting package includes one or more areas of conductive material having a thickness of less than approximately 50 microns (μm). The package can further include at least one light... http://www.freshpatents.com/-dt20130516ptan20130119420.php Mon, 20 May 2013 13:35:02 -0700 A light emitting device is disclosed. The light emitting device includes an electrode, which includes a reflective electrode layer disposed over a second semiconductor layer and a bonding electrode layer disposed in at least a partial region of an outer side surface of the reflective electrode layer while coming into... http://www.freshpatents.com/-dt20130516ptan20130119424.php Mon, 20 May 2013 13:35:02 -0700 A light emitting device is provided a transmissive substrate; a first pattern portion including a protrusions; a second pattern portion including a concaves having a width smaller than a width of each protrusion; a light emitting structure under the transmissive substrate and including a first conductive semiconductor layer, a second... http://www.freshpatents.com/-dt20130516ptan20130119421.php Mon, 20 May 2013 13:35:02 -0700 An LED epitaxial structure includes a substrate, a buffer layer, a functional layer and a light generating layer. The buffer layer is located on a top surface of the substrate. The functional layer includes a plurality of high-temperature epitaxial layers and low-temperature epitaxial layers alternatively arranged between the buffer layer... http://www.freshpatents.com/-dt20130516ptan20130119425.php Mon, 20 May 2013 13:35:02 -0700 An object of the present invention is to provide a light emitting element having slight increase in driving voltage with accumulation of light emitting time. Another object of the invention is to provide a light emitting element having slight increase in resistance value with increase in film thickness. A light... http://www.freshpatents.com/-dt20130516ptan20130119426.php Mon, 20 May 2013 13:35:02 -0700 A low-cost and productivity-oriented surface mount light-emitting device is provided. The light-emitting device includes an insulating film 2, at least one pair of land portions 3a and 3b comprising metal film pieces formed on the top surface of the insulating film 2, external connection terminal portions 4a and 4b comprising... http://www.freshpatents.com/-dt20130516ptan20130119419.php Mon, 20 May 2013 13:35:02 -0700 Magnetically adjusting color-converting particles within a matrix and associated devices, systems, and methods are disclosed herein. A magnetic-adjustment process can include applying a magnetic field to a mixture including a non-solid matrix and a plurality of color-converting particles (e.g. magnetically anisotropic color-converting particles). The magnetic field can cause the plurality... http://www.freshpatents.com/-dt20130516ptan20130119418.php Mon, 20 May 2013 13:35:02 -0700 A method of forming can be provided by applying an optical conversion material to a mold to form a unitary layer of optical conversion material and removing the unitary layer of optical conversion material from the mold.... http://www.freshpatents.com/-dt20130516ptan20130119423.php Mon, 20 May 2013 13:35:02 -0700 A semiconductor light emitting device and package containing the same include: a light emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer. A light extraction layer is disposed on the light emitting structure and includes a light-transmissive thin film layer having light... http://www.freshpatents.com/-dt20130516ptan20130119422.php Mon, 20 May 2013 13:35:02 -0700 A semiconductor light emitting device has a multilayer epitaxial structure for emitting light by a light emitting layer located between a first conductive layer and a second conductive layer. The multilayer epitaxial structure can be grown directly on a base substrate. A reflective layer can be provided in the multilayer... http://www.freshpatents.com/-dt20130516ptan20130119427.php Mon, 20 May 2013 13:35:02 -0700 An LED substrate may comprise a base including a first surface and a second surface; and a conductive structure formed on at least a part of the first surface and at least a part of the second surface, the part of the conductive structure formed on the first surface electrically... http://www.freshpatents.com/-dt20130516ptan20130119430.php Mon, 20 May 2013 13:35:02 -0700 Provided are a vertical-type light emitting device and a method of manufacturing the same. The light emitting device includes a p-type semiconductor layer, an active layer, and an n-type semi-conductor layer that are stacked, a cover layer disposed on a p-type electrode layer to surround the p-type electrode layer, a... http://www.freshpatents.com/-dt20130516ptan20130119429.php Mon, 20 May 2013 13:35:02 -0700 A light-emitting element includes a light-emitting stack includes: a first semiconductor layer; an active layer formed on the first semiconductor layer; and a second semiconductor layer formed on the active layer; a recess structure formed through the second semiconductor layer, the active layer, and extended in the first semiconductor layer,... http://www.freshpatents.com/-dt20130516ptan20130119428.php Mon, 20 May 2013 13:35:02 -0700 The present invention provides a light-emitting element, a light-emitting device and an electronic device in which an optical path length through which generated light goes can be changed easily. The present invention provides a light-emitting element including a light-emitting layer between a first electrode and a second electrode, and a... http://www.freshpatents.com/-dt20130516ptan20130119431.php Mon, 20 May 2013 13:35:02 -0700 Provided is a light emitting module in which an LED device is mounted and power is supplied to the LED device by a gold wire. The light emitting module includes a first resin (sealing material) that seals the gold wire and a second resin (dam wall) that surrounds at least... http://www.freshpatents.com/-dt20130516ptan20130119432.php Mon, 20 May 2013 13:35:02 -0700 A semiconductor device having a p+ collector region in the surface of an n− drift region. The p+ collector region forms a p-n junction with the n− drift region. A collector electrode is in contact with the p+ collector region. A low-lifetime region having a carrier lifetime shorter than in... http://www.freshpatents.com/-dt20130516ptan20130119433.php Mon, 20 May 2013 13:35:02 -0700 Among other things, an electrostatic discharge (ESD) device is provided. The ESD device comprises a dielectric isolation structure that is formed between an emitter and a collector of the ESD device. During an ESD event, current flows from the emitter, substantially under the dielectric isolation structure, to the collector, to... http://www.freshpatents.com/-dt20130516ptan20130119434.php Mon, 20 May 2013 13:35:02 -0700 Disclosed are embodiments of a transistor (e.g., bipolar junction transistor (BJT) or a heterojunction bipolar transistor (HBT)) and a method of forming the transistor with a collector region having a protected upper edge portion for reduced base-collector junction capacitance Cbc. In the embodiments, a collector region is positioned laterally adjacent... http://www.freshpatents.com/-dt20130516ptan20130119435.php Mon, 20 May 2013 13:35:02 -0700 An integrated device includes a lower layer pattern on a semiconductor substrate. The lower layer pattern includes a first region including first electrical devices and a second region including second electrical devices and electrically nonconductive dummy devices. A first device density of the first electrical devices in the first region... http://www.freshpatents.com/-dt20130516ptan20130119436.php Mon, 20 May 2013 13:35:02 -0700 Methods of fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. A first portion of the intrinsic base layer is masked while a second portion of an intrinsic base layer is etched. As a consequence of the masking, the second portion of the intrinsic... http://www.freshpatents.com/-dt20130516ptan20130119437.php Mon, 20 May 2013 13:35:02 -0700 A semiconductor device having small leakage current and high breakdown voltage during reverse blocking, small on-state resistance and large output current at forward conduction, short reverse recovery time at shutoff, and high peak surge current value is provided. An n-type layer is made of a group-III nitride, and a p-type... http://www.freshpatents.com/-dt20130516ptan20130119438.php Mon, 20 May 2013 13:35:02 -0700 A unit pixel of a depth sensor including a light-intensity output circuit configured to output a pixel signal according to a control signal, the pixel signal corresponding to a first electric charge and a second electric charge, a first light-intensity extraction circuit configured to generate the first electric charge and... http://www.freshpatents.com/-dt20130516ptan20130119439.php Mon, 20 May 2013 13:35:02 -0700 A method of producing a solid-state image pickup apparatus, including the steps of: forming a plurality of light-receiving portions on a substrate; forming a plurality of transfer gates to be connected to the plurality of light-receiving portions formed on the substrate; forming an insulation film on the substrate; exposing a... http://www.freshpatents.com/-dt20130516ptan20130119440.php Mon, 20 May 2013 13:35:02 -0700 A biosensor with a microfluidic structure surrounded by an electrode and methods of forming the electrode around the microfluidic structure of the biosensor are provided. A method includes forming a gate or electrode in a first layer. The method further includes forming a trench in a second layer. The method... http://www.freshpatents.com/-dt20130516ptan20130119441.php Mon, 20 May 2013 13:35:02 -0700 A microelectronic device including a substrate, at least a semi-conductor element, an anti metal ion layer, a non-doping oxide layer and a MEMS structure is provided. The substrate has a CMOS circuit region and a MEMS region. The semi-conductor element is configured within the CMOS circuit region of the substrate.... http://www.freshpatents.com/-dt20130516ptan20130119442.php Mon, 20 May 2013 13:35:02 -0700 Junction field-effect transistors, methods for fabricating junction field-effect transistors, and design structures for a junction field-effect transistor. A source and a drain of the junction field-effect transistor are comprised of a semiconductor material grown by selective epitaxy and in direct contact with a top surface of a semiconductor layer. A... http://www.freshpatents.com/-dt20130516ptan20130119443.php Mon, 20 May 2013 13:35:02 -0700 The invention relates to a structure comprising an n-type substrate (1) having a bottom surface (10) and a top surface (11), a drain (D) contacting the bottom surface (10) of the substrate (1), a first n-type semiconductor region (2) having a top surface (21) provided with a contact area (210),... http://www.freshpatents.com/-dt20130516ptan20130119445.php Mon, 20 May 2013 13:35:02 -0700 A CMOS device for reducing a radiation-induced charge collection and a method for fabricating the same. In the CMOS device, a heavily doped charge collection-suppressed region is disposed directly under the source region and the drain region. The region has a doping type opposite that of the source region and... http://www.freshpatents.com/-dt20130516ptan20130119446.php Mon, 20 May 2013 13:35:02 -0700 An electrical device in which an interface layer comprising arsenic is disposed between and in contact with a conductor and a semiconductor. In some cases, the interface layer may be a monolayer of arsenic.... http://www.freshpatents.com/-dt20130516ptan20130119444.php Mon, 20 May 2013 13:35:02 -0700 An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. The disclosed method comprises forming a wedge-shaped recess with an initial bottom surface in the substrate; transforming the wedge-shaped recess into an enlarged recess with a height greater than the height of the wedge-shaped recess; and... http://www.freshpatents.com/-dt20130516ptan20130119447.php Mon, 20 May 2013 13:35:02 -0700 A non-uniform gate dielectric charge for pixel sensor cells, e.g., CMOS optical imagers, and methods of manufacturing are provided. The method includes forming a gate dielectric on a substrate. The substrate includes a source/drain region and a photo cell collector region. The method further includes forming a non-uniform fixed charge... http://www.freshpatents.com/-dt20130516ptan20130119448.php Mon, 20 May 2013 13:35:02 -0700 A memory array layout includes an active region array having a plurality of active regions, wherein the active regions are arranged alternatively along a second direction and parts of the side of the adjacent active regions are overlapped along a second direction; a plurality of first doped region, wherein each... http://www.freshpatents.com/-dt20130516ptan20130119449.php Mon, 20 May 2013 13:35:02 -0700 A seal ring for semiconductor devices is provided with embedded decoupling capacitors. The seal ring peripherally surrounds an integrated circuit chip in a seal ring area. The at least one embedded decoupling capacitor may include MOS capacitors, varactors, MOM capacitors and interdigitized capacitors with multiple capacitor plates coupled together. The... http://www.freshpatents.com/-dt20130516ptan20130119450.php Mon, 20 May 2013 13:35:02 -0700 Provided is a non-volatile semiconductor storage device including a memory cell which is disposed on a semiconductor substrate and where a control gate electrode is disposed on a charge storage layer, a select gate transistor where a select gate electrode is disposed between a source region and a drain region... http://www.freshpatents.com/-dt20130516ptan20130119451.php Mon, 20 May 2013 13:35:02 -0700 In some embodiments, an interlayer polysilicon dielectric cap disposed atop a substrate having a first floating gate, a second floating gate and an isolation layer disposed between the first floating gate and the second floating gate may include: a first nitrogen containing layer disposed atop an upper portion and sidewalls... http://www.freshpatents.com/-dt20130516ptan20130119454.php Mon, 20 May 2013 13:35:02 -0700 One end of an electricity supply line ESL is arranged over a terminal end TE1 and the other end thereof is arranged over a terminal end TE2, and further, the central portion of the electricity supply line ESL is arranged over a dummy part DMY. That is, the terminal end... http://www.freshpatents.com/-dt20130516ptan20130119453.php Mon, 20 May 2013 13:35:02 -0700 A non-volatile memory unit cell includes a transistor pair, and first, second, third and fourth control gates. The transistor pair has a first transistor and a second transistor that are connected in parallel and of opposite types. The first transistor and the second transistor have a first floating polysilicon gate... http://www.freshpatents.com/-dt20130516ptan20130119452.php Mon, 20 May 2013 13:35:02 -0700 Provided is a semiconductor integrated circuit that uses a novel vertical MOS transistor that is free of interference between cells, that enables the short-channel effect to be minimized, that does not have hot electron injection, and that does not require the formation of shallow junction. Also provided is a method... http://www.freshpatents.com/-dt20130516ptan20130119457.php Mon, 20 May 2013 13:35:02 -0700 A memory device, a manufacturing method and an operating method of the same are provided. The memory device includes a substrate, stacked structures, a channel element, a dielectric element, a source element, and a bit line. The stacked structures are disposed on the substrate. Each of the stacked structures includes... http://www.freshpatents.com/-dt20130516ptan20130119455.php Mon, 20 May 2013 13:35:02 -0700 A manufacturing method for a memory array includes first forming a multilayer stack of dielectric material on a plurality of semiconductor strips, and then exposing the multilayer stack in switch transistor regions. The multilayer stacks exposed in the switch transistor regions are processed to form gate dielectric structures that are... http://www.freshpatents.com/-dt20130516ptan20130119456.php Mon, 20 May 2013 13:35:02 -0700 According to one embodiment, a semiconductor device includes: a substrate; a stacked body provided above the substrate, including a selector gate and an insulating layer provided on the selector gate; an insulating film provided on a sidewall of a hole formed by penetrating the stacked body in the stacking direction;... http://www.freshpatents.com/-dt20130516ptan20130119458.php Mon, 20 May 2013 13:35:02 -0700 The present invention provides a NOR flash memory cell. The NOR flash memory cell includes a a substrate, an active area, a first gate structure, a second gate structure and at least one third gate structure. The first gate structure covers a first partial region of the active area and... http://www.freshpatents.com/-dt20130516ptan20130119459.php Mon, 20 May 2013 13:35:02 -0700 A semiconductor device and a method for manufacturing the same are disclosed, which form a bit line only at one side of a line pattern by partially etching a semiconductor substrate in a vertical gate structure, such that a body tied structure for reducing the floating body effect can be... http://www.freshpatents.com/-dt20130516ptan20130119461.php Mon, 20 May 2013 13:35:02 -0700 A semiconductor device includes: a first interlayer insulating layer in first and second regions of a semiconductor substrate, a second interlayer insulating layer over the first interlayer insulating layer in first and second regions, a hard mask provided between the first and the second interlayer insulating layers in the second... http://www.freshpatents.com/-dt20130516ptan20130119460.php Mon, 20 May 2013 13:35:02 -0700 The present invention provides a trench type power transistor device including a substrate, an epitaxial layer, a doped diffusion region, a doped source region, and a gate structure. The substrate, the doped diffusion region, and the doped source region have a first conductivity type, and the substrate has an active... http://www.freshpatents.com/-dt20130516ptan20130119463.php Mon, 20 May 2013 13:35:02 -0700 A semiconductor device and a method for manufacturing the same are provided. The method includes forming a cell structure where a storage node contact is coupled to a silicon layer formed over a gate, thereby simplifying the manufacturing process of the device. The semiconductor device includes a bit line buried... http://www.freshpatents.com/-dt20130516ptan20130119462.php Mon, 20 May 2013 13:35:02 -0700 A semiconductor device including a buried gate is disclosed. In the semiconductor device, a bit line contact contacts a top surface and lateral surfaces of an active region, such that a contact area between a bit line contact and the active region is increased and a high-resistivity failure is prevented... http://www.freshpatents.com/-dt20130516ptan20130119464.php Mon, 20 May 2013 13:35:02 -0700 A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second layer over the first conductive layer, forming a plurality of active regions by etching the second layer and the first conductive... http://www.freshpatents.com/-dt20130516ptan20130119465.php Mon, 20 May 2013 13:35:02 -0700 A dual channel trench LDMOS transistor includes a semiconductor layer of a first conductivity type formed on a substrate; a first trench formed in the semiconductor layer where a trench gate is formed in an upper portion of the first trench; a body region of the second conductivity type formed... http://www.freshpatents.com/-dt20130516ptan20130119466.php Mon, 20 May 2013 13:35:02 -0700 A semiconductor device is provided which includes a semiconductor substrate, a gate structure formed on the substrate, sidewall spacers formed on each side of the gate structure, a source and a drain formed in the substrate on either side of the gate structure, the source and drain having a first... http://www.freshpatents.com/-dt20130516ptan20130119467.php Mon, 20 May 2013 13:35:02 -0700 A DMOS transistor is fabricated with its source/body/deep body regions formed on the walls of a first set of trenches, and its drain regions formed on the walls of a different set of trenches. A gate region that is formed in a yet another set of trenches can be biased... http://www.freshpatents.com/-dt20130516ptan20130119471.php Mon, 20 May 2013 13:35:02 -0700 A display panel includes; a substrate, and a light blocking structure surrounding an ink filling region on the substrate, the light blocking structure including; a first layer pattern having an ink affinity characteristic disposed on the substrate, and a second layer pattern positioned on the first layer pattern and including... http://www.freshpatents.com/-dt20130516ptan20130119469.php Mon, 20 May 2013 13:35:02 -0700 Improvements are achieved in the characteristics of a semiconductor device including SRAM memory cells. Under an active region in which an access transistor forming an SRAM is disposed, a p-type semiconductor region is disposed via an insulating layer such that the bottom portion and side portions thereof come in contact... http://www.freshpatents.com/-dt20130516ptan20130119470.php Mon, 20 May 2013 13:35:02 -0700 Characteristics of a semiconductor device are improved. A semiconductor device of the present invention includes: (a) a MISFET arranged in an active region formed of a semiconductor region surrounded by an element isolation region; and (b) an insulating layer arranged below the active region. Further, the semiconductor device includes: (c)... http://www.freshpatents.com/-dt20130516ptan20130119468.php Mon, 20 May 2013 13:35:02 -0700 A thin-film transistor may include a drain electrode, a source electrode, an active layer, a gate electrode, and a gate insulating layer. In a vertical sectional view, the gate insulating layer may be disposed between the active layer and the gate electrode to include a first inorganic layer, an organic... http://www.freshpatents.com/-dt20130516ptan20130119472.php Mon, 20 May 2013 13:35:02 -0700 Provided is a semiconductor device comprising: a PW layer formed at a surface of a semiconductor substrate; an NW layer formed at the surface of the semiconductor substrate to be in contact with the PW layer; a p+ base layer formed at the surface of the semiconductor substrate in the... http://www.freshpatents.com/-dt20130516ptan20130119473.php Mon, 20 May 2013 13:35:02 -0700 A metal gate structure with a channel material and methods of manufacture such structure is provided. The method includes forming dummy gate structures on a substrate. The method further includes forming sidewall structures on sidewalls of the dummy gate structures. The method further includes removing the dummy gate structures to... http://www.freshpatents.com/-dt20130516ptan20130119476.php Mon, 20 May 2013 13:35:02 -0700 A semiconductor device includes a cross-coupled transistor configuration formed by first and second PMOS transistors defined over first and second p-type diffusion regions, and by first and second NMOS transistors defined over first and second n-type diffusion regions, with each diffusion region electrically connected to a common node. Gate electrodes... http://www.freshpatents.com/-dt20130516ptan20130119475.php Mon, 20 May 2013 13:35:02 -0700 A method for designing a semiconductor device includes arranging at least a pattern of a first active region in which a first transistor is formed and a pattern of a second active region in which a second transistor is formed; arranging at least a pattern of a gate wire which... http://www.freshpatents.com/-dt20130516ptan20130119474.php Mon, 20 May 2013 13:35:02 -0700 A semiconductor device fabrication process includes forming insulating mandrels over replacement metal gates on a semiconductor substrate with first gates having sources and drains and at least one second gate being isolated from the first gates. Mandrel spacers are formed around each insulating mandrel. The mandrels and mandrel spacers include... http://www.freshpatents.com/-dt20130516ptan20130119477.php Mon, 20 May 2013 13:35:02 -0700 A semiconductor device includes a first fin formed of a first semiconductor material and a second fin comprising a layer formed of a second semiconductor material. The first semiconductor material is silicon, and the second semiconductor material is silicon-germanium (SiGe). The second fin further includes a layer of the first... http://www.freshpatents.com/-dt20130516ptan20130119478.php Mon, 20 May 2013 13:35:02 -0700 A semiconductor device is described as including a first fin having a layer formed of a first semiconductor material and a second fin that is formed of a second semiconductor material. The first and second semiconductor materials are different. The second semiconductor material may have a mobility of P-type carriers... http://www.freshpatents.com/-dt20130516ptan20130119479.php Mon, 20 May 2013 13:35:02 -0700 A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a N-type well, a gate disposed on the N-type well, a spacer disposed on the gate, a first lightly doped region in the substrate below the spacer, a P-type source/drain region disposed in the... http://www.freshpatents.com/-dt20130516ptan20130119480.php Mon, 20 May 2013 13:35:02 -0700 A semiconductor device includes a substrate including an isolation region, and a resistor disposed over the isolation region, wherein the resistor includes an implant with an inverse box-like dopant profile that minimizes resistance variation from subsequent planarization variation. A contact is disposed over the resistor. A method of fabricating such... http://www.freshpatents.com/-dt20130516ptan20130119482.php Mon, 20 May 2013 13:35:02 -0700 The disclosure relates to a Fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a top surface; a first fin and a second fin extending above the substrate top surface, wherein each of the fins has a top surface and sidewalls; an insulation layer... http://www.freshpatents.com/-dt20130516ptan20130119481.php Mon, 20 May 2013 13:35:02 -0700 A method for forming a field effect transistor device includes patterning an arrangement of fin portions on a substrate, patterning a gate stack portion over portions of the fin portions and the substrate, growing an epitaxial material from the fin portions that electrically connects portions of adjacent fin structures, and... http://www.freshpatents.com/-dt20130516ptan20130119483.php Mon, 20 May 2013 13:35:02 -0700 A structure and method for fabricating silicide contacts for semiconductor devices is provided. Specifically, the structure and method involves utilizing chemical vapor deposition (CVD) and annealing to form silicide contacts of different shapes, selectively on regions of a semiconductor field effect transistor (FET), such as on source and drain regions.... http://www.freshpatents.com/-dt20130516ptan20130119484.php Mon, 20 May 2013 13:35:02 -0700 The present invention provides a method of manufacturing a semiconductor device comprising: providing a semiconductor substrate, on which a high-k dielectric layer and a patterned gate are formed sequentially; nitridating portions of the high-k dielectric layer on the semiconductor substrate which are not covered by the gate; and forming spacers... http://www.freshpatents.com/-dt20130516ptan20130119485.php Mon, 20 May 2013 13:35:02 -0700 The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a first metal layer on the high k dielectric material layer; forming a silicon layer on the first metal layer;... http://www.freshpatents.com/-dt20130516ptan20130119486.php Mon, 20 May 2013 13:35:02 -0700 A nitride semiconductor device includes a nitride semiconductor multilayer including an active region, and first and second electrodes, each having a finger-like structure and formed on the active region to be spaced from each other. A first electrode interconnect is formed on the first electrode. A second electrode interconnect is... http://www.freshpatents.com/-dt20130516ptan20130119487.php Mon, 20 May 2013 13:35:02 -0700 The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate; and a gate stack disposed on the semiconductor substrate. The gate stack includes a high k dielectric material layer, a capping layer disposed on the high k dielectric material layer, and a metal layer disposed on... http://www.freshpatents.com/-dt20130516ptan20130119488.php Mon, 20 May 2013 13:35:02 -0700 An electronic device may include a housing with a connector member opening therein, electronic circuitry within the housing, and a finger sensor assembly carried by the housing. The finger assembly may include a thinned finger sensing integrated circuit (IC) secured to the housing that has a thickness less than 200... http://www.freshpatents.com/-dt20130516ptan20130119489.php Mon, 20 May 2013 13:35:02 -0700 A plurality of MEMS devices are formed on a substrate, a sacrificial layer is formed to cover each of the MEMS devices and a protective cap layer is formed on the sacrificial layer. A release hole is formed through the protective cap layer to the underlying sacrificial layer, and a... http://www.freshpatents.com/-dt20130516ptan20130119491.php Mon, 20 May 2013 13:35:02 -0700 Bulk acoustic wave filters and/or bulk acoustic resonators integrated with CMOS processes, methods of manufacture and design structures are disclosed. The method includes forming at least one beam comprising amorphous silicon material and providing an insulator material over and adjacent to the amorphous silicon beam. The method further includes forming... http://www.freshpatents.com/-dt20130516ptan20130119490.php Mon, 20 May 2013 13:35:02 -0700 Bulk acoustic wave filters and/or bulk acoustic resonators integrated with CMOS devices, methods of manufacture and design structure are provided. The method includes forming a single crystalline beam from a silicon layer on an insulator. The method further includes providing a coating of insulator material over the single crystalline beam.... http://www.freshpatents.com/-dt20130516ptan20130119492.php Mon, 20 May 2013 13:35:02 -0700 The invention relates to a miniaturized electrical component comprising an MEMS chip and an ASIC chip. The MEMS chip and the ASIC chip are disposed on top of each other; an internal mounting of MEMS chip and ASIC chip is connected to external electrical terminals of the electrical component by... http://www.freshpatents.com/-dt20130516ptan20130119493.php Mon, 20 May 2013 13:35:02 -0700 A microelectro mechanical system (MEMS) assembly includes a carrier and a MEMS device disposed over the carrier. A buffer layer is disposed over the MEMS device. The Young's modulus of the buffer layer is less than that of the MEMS device.... http://www.freshpatents.com/-dt20130516ptan20130119495.php Mon, 20 May 2013 13:35:02 -0700 Semiconductor stack structures such as magnetic tunnel junction structures having a magnetic free layer that is grown on composite, obliquely deposited seed layers to induce an increased in-plane magnetic anisotropy Hk of the magnetic free layer. In one aspect, a semiconductor device includes a composite seed layer formed on a... http://www.freshpatents.com/-dt20130516ptan20130119497.php Mon, 20 May 2013 13:35:02 -0700 A magnetic tunnel junction (MTJ) device is formed by a process that includes forming a trench in a substrate and depositing an MTJ structure within the trench. The MTJ structure includes a bottom electrode, a fixed layer, a tunnel barrier layer, a free layer, and a top electrode. The process... http://www.freshpatents.com/-dt20130516ptan20130119498.php Mon, 20 May 2013 13:35:02 -0700 A spin-torque transfer magnetic random access memory (STTMRAM) element employed to store a state based on the magnetic orientation of a free layer, the STTMRAM element is made of a first perpendicular free layer (PFL) including a first perpendicular enhancement layer (PEL). The first PFL is formed on top of... http://www.freshpatents.com/-dt20130516ptan20130119494.php Mon, 20 May 2013 13:35:02 -0700 A memory device may comprise a magnetic tunnel junction (MTJ) stack, a bottom electrode (BE) layer, and a contact layer. The MTJ stack may include a free layer, a barrier, and a pinned layer. The BE layer may be coupled to the MTJ stack, and encapsulated in a planarized layer.... http://www.freshpatents.com/-dt20130516ptan20130119496.php Mon, 20 May 2013 13:35:02 -0700 The present disclosure describes a semiconductor MRAM device and a manufacturing method. The device reduces magnetic field induction “interference” (disturbance) phenomenon between adjacent magnetic tunnel junctions when data is written and read. This semiconductor MRAM device comprises a magnetic tunnel junction unit and a magnetic shielding material layer covering the... http://www.freshpatents.com/-dt20130516ptan20130119499.php Mon, 20 May 2013 13:35:02 -0700 Apparatus, compositions, methods, and articles of manufacture are disclosed relating to the design and production of biological components and/or their incorporation in devices and systems, including biohybrid photosensitive devices and systems. In some embodiments, biological components include light antenna structures that collect light and emit Stokes-shifted light to a photoactive... http://www.freshpatents.com/-dt20130516ptan20130119501.php Mon, 20 May 2013 13:35:02 -0700 An image pickup apparatus includes: an image pickup device disposed in a first principal surface of a silicon substrate, the image pickup device sensing infrared light; an electrode pad disposed on the first principal surface; a front-face wiring connecting the image pickup device and the electrode pad; an external connection... http://www.freshpatents.com/-dt20130516ptan20130119500.php Mon, 20 May 2013 13:35:02 -0700 Provided is a semiconductor image sensor device. The image sensor device includes a semiconductor substrate that includes an array region and a black level correction region. The array region contains a plurality of radiation-sensitive pixels. The black level correction region contains one or more reference pixels. The substrate has a... http://www.freshpatents.com/-dt20130516ptan20130119503.php Mon, 20 May 2013 13:35:02 -0700 The substrate includes successively a first semiconductor layer having a first bandgap energy, a semiconductor buffer layer, a second semiconductor layer having a first bandgap energy different from the first bandgap energy. Two photodetectors sensitive to two different colors are formed respectively on the first and second semiconductor layers. A... http://www.freshpatents.com/-dt20130516ptan20130119502.php Mon, 20 May 2013 13:35:02 -0700 A semiconductor device formed on a substrate includes a first diode junction formation, a second diode junction formation, and at least one through-silicon-via (TSV), in which a cathode and an anode of the first diode are cross-connected to an anode and cathode of the second diode through the at least... http://www.freshpatents.com/-dt20130516ptan20130119504.php Mon, 20 May 2013 13:35:02 -0700 An object of the present invention is to provide a thermal airflow sensor that prevents moisture absorption by a silicon oxide film formed closest to a surface (formed to be located on an uppermost portion), and that reduces a measuring error. In order to attain the foregoing object, the thermal... http://www.freshpatents.com/-dt20130516ptan20130119505.php Mon, 20 May 2013 13:35:02 -0700 Schottky barrier diodes, methods for fabricating Schottky barrier diodes, and design structures for a Schottky barrier diode. A guard ring for a Schottky barrier diode is formed with a selective epitaxial growth process. The guard ring for the Schottky barrier diode and an extrinsic base of a vertical bipolar junction... http://www.freshpatents.com/-dt20130516ptan20130119506.php Mon, 20 May 2013 13:35:02 -0700 Methods and structure are provided to facilitate isolation of respective ground plane regions in an SOTB semiconductor device. In one aspect a shallow STI trench can be combined with Si:C or Si:C/SiGe layers to confine n-type and p-type regions. In a further aspect, Ge can be implanted at the bottom... http://www.freshpatents.com/-dt20130516ptan20130119507.php Mon, 20 May 2013 13:35:02 -0700 Semiconductor devices using a group III-V material, and methods of manufacturing the same, include a substrate having a groove, a group III-V material layer filling in the groove and having a height the same as a height of the substrate, a first semiconductor device on the group III-V material layer,... http://www.freshpatents.com/-dt20130516ptan20130119508.php Mon, 20 May 2013 13:35:02 -0700 Methods for fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. The bipolar junction transistor may include a plurality of emitters that are arranged in distinct emitter fingers. A silicide layer is formed that covers an extrinsic base layer of the bipolar junction transistor... http://www.freshpatents.com/-dt20130516ptan20130119509.php Mon, 20 May 2013 13:35:02 -0700 In one embodiment, the invention provides a back-end-of-line (BEOL) line fuse structure. The BEOL line fuse structure includes: a line including a plurality of grains of conductive crystalline material; wherein the plurality of grains in a region between the first end and a second end include an average grain size... http://www.freshpatents.com/-dt20130516ptan20130119510.php Mon, 20 May 2013 13:35:02 -0700 A device is provided that includes a vertically oriented p-i-n diode that includes semiconductor material, a silicide, germanide, or silicide-germanide layer disposed adjacent the vertically oriented p-i-n diode, and a dielectric material arranged electrically in series with the vertically oriented p-i-n diode. The dielectric material is disposed between a first... http://www.freshpatents.com/-dt20130516ptan20130119511.php Mon, 20 May 2013 13:35:02 -0700 The present application discloses an inductor including a substrate, a first conductive line and a second conductive line formed over the substrate, a passivation layer formed over the first and the second conductive lines, and a bond wire coupling an end of the first conductive line and an end of... http://www.freshpatents.com/-dt20130516ptan20130119513.php Mon, 20 May 2013 13:35:02 -0700 A method for doping a dielectric material by pulsing a first dopant precursor, purging the non-adsorbed precursor, pulsing a second precursor, purging the non-adsorbed precursor, and pulsing a oxidant to form an intermixed layer of two (or more) metal oxide dielectric dopant materials. The method may also be used to... http://www.freshpatents.com/-dt20130516ptan20130119515.php Mon, 20 May 2013 13:35:02 -0700 A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode film. The first electrode film comprises a conductive binary metal compound and a dopant. The dopant may have a uniform or non-uniform concentration within the first electrode film. A high-k dielectric film is formed... http://www.freshpatents.com/-dt20130516ptan20130119514.php Mon, 20 May 2013 13:35:02 -0700 A method for manufacturing a semiconductor device includes at least forming a lower electrode comprising titanium nitride on a semiconductor substrate, forming a dielectric film comprising zirconium oxide as a primary constituent on the lower electrode, forming a first protective film comprising a titanium compound on the dielectric film, and... http://www.freshpatents.com/-dt20130516ptan20130119512.php Mon, 20 May 2013 13:35:02 -0700 A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized... http://www.freshpatents.com/-dt20130516ptan20130119516.php Mon, 20 May 2013 13:35:02 -0700 Lateral PNP bipolar junction transistors, methods for fabricating lateral PNP bipolar junction transistors, and design structures for a lateral PNP bipolar junction transistor. An emitter and a collector of the lateral PNP bipolar junction transistor are comprised of p-type semiconductor material that is formed by a selective epitaxial growth process.... http://www.freshpatents.com/-dt20130516ptan20130119519.php Mon, 20 May 2013 13:35:02 -0700 Provided are a composite substrate which includes a silicon substrate having improved crystallinity, a method for manufacturing a composite substrate, and a method for manufacturing an electronic component. A composite substrate is formed by bonding a semiconductor substrate onto a support substrate having electric insulating properties. The semiconductor substrate is... http://www.freshpatents.com/-dt20130516ptan20130119517.php Mon, 20 May 2013 13:35:02 -0700 In one embodiment, a method of forming a semiconductor device includes forming islands by forming deep trenches within scribe lines of a substrate. The islands have a first notch disposed on sidewalls of the islands. A first electrode stack is formed over a top surface of the islands. The back... http://www.freshpatents.com/-dt20130516ptan20130119518.php Mon, 20 May 2013 13:35:02 -0700 A method for growing semiconductor wafers by lateral diffusion liquid phase epitaxy is described. Also provided are a refractory device for practicing the disclosed method and semiconductor wafers prepared by the disclosed method and device. The disclosed method and device allow for significant cost and material waste savings over current... http://www.freshpatents.com/-dt20130516ptan20130119520.php Mon, 20 May 2013 13:35:02 -0700 A microelectronic element is disclosed that includes a semiconductor chip and a continuous monolithic metallic edge-reinforcement ring that covers each of the plurality of edge surfaces of the semiconductor chip and extending onto the front surface. The semiconductor chip may have front and rear opposed surfaces and a plurality of... http://www.freshpatents.com/-dt20130516ptan20130119521.php Mon, 20 May 2013 13:35:02 -0700 A semiconductor substrate having a through-silicon via with an air gap interposed between the through-silicon via and the semiconductor substrate is provided. An opening is formed partially through the semiconductor substrate. The opening is first lined with a first liner and then the opening is filled with a conductive material.... http://www.freshpatents.com/-dt20130516ptan20130119522.php Mon, 20 May 2013 13:35:02 -0700 A semiconductor substrate includes a first side and a second side opposite the first side. A semiconductor material extends between the first and second sides and is devoid of active device regions. The semiconductor material has a first region and a second region. The first region extends from the first... http://www.freshpatents.com/-dt20130516ptan20130119523.php Mon, 20 May 2013 13:35:02 -0700 A packaging structure includes: a substrate (21), where the substrate (21) is arranged with a grounding end (27) and at least two circuit modules; a shielding separator (24) connected to the substrate (21) for separating the at least two circuit modules; a packaging insulator (25) applied on the substrate (21)... http://www.freshpatents.com/-dt20130516ptan20130119524.php Mon, 20 May 2013 13:35:02 -0700 A chip package includes: a substrate having a first surface and a second surface; a device region disposed in or on the substrate; a conducting pad disposed in the substrate or on the first surface, wherein the conducting pad is electrically connected to the device region; a hole extending from... http://www.freshpatents.com/-dt20130516ptan20130119525.php Mon, 20 May 2013 13:35:02 -0700 Heat radiation surfaces 7b and 8b of electrode lead frames 7 and 8 make thermal contact with heat radiation members 301 via insulation sheets 10 to dissipate heat from a power semiconductor element 5 to the heat radiation members (thick portions 301). Each of exposed areas of the heat radiation... http://www.freshpatents.com/-dt20130516ptan20130119526.php Mon, 20 May 2013 13:35:02 -0700 According to one embodiment, a lead frame includes a die pad having a mounting surface on which a semiconductor chip is mounted, plural leads having inner leads and outer leads, and a connecting member that extends from the die pad to both ends of a plurality of leads and connects... http://www.freshpatents.com/-dt20130516ptan20130119527.php Mon, 20 May 2013 13:35:02 -0700 A semiconductor die assembly comprises a plurality of semiconductor dice in a stack. Another semiconductor die is adjacent to the stack and has a region, which may comprise a relatively higher power density region, extends peripherally beyond the stack. Conductive elements extend between and electrically interconnect integrated circuits of semiconductor... http://www.freshpatents.com/-dt20130516ptan20130119528.php Mon, 20 May 2013 13:35:02 -0700 Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can... http://www.freshpatents.com/-dt20130516ptan20130119529.php Mon, 20 May 2013 13:35:02 -0700 A semiconductor device includes a substrate, a first die attached to the substrate, and a lid coupled to the substrate. The lid defines a cavity for engaging the first die, and the lid has a die enclosure barrier having ends extending downwardly into the cavity. The ends of the die... http://www.freshpatents.com/-dt20130516ptan20130119530.php Mon, 20 May 2013 13:35:02 -0700 A thermally enhanced packaging structure includes a chip carrier; a high power chip disposed on the chip carrier; a molding compound covering the high power chip; a heat dissipating layer disposed on the molding compound, wherein the heat dissipating layer comprises a plurality of carbon nanocapsules (CNCs); and a non-fin... http://www.freshpatents.com/-dt20130516ptan20130119531.php Mon, 20 May 2013 13:35:02 -0700 According to one embodiment, a method for manufacturing a semiconductor device includes: forming an underlayer film that contains atoms selected from the group consisting of aluminum, boron and alkaline earth metal; and forming a silicon oxide film on the underlayer film by a CVD method or an ALD method by... http://www.freshpatents.com/-dt20130516ptan20130119532.php Mon, 20 May 2013 13:35:02 -0700 A chip scale semiconductor device comprises a semiconductor die, a first bump and a second bump. The first bump having a first diameter and a first height is formed on an outer region of the semiconductor die. A second bump having a second diameter and a second height is formed... http://www.freshpatents.com/-dt20130516ptan20130119535.php Mon, 20 May 2013 13:35:02 -0700 Systems and methods for improving thermal performance, such as thermal dissipation, of flip chip packages that include one or more flip chip dies are disclosed. In some embodiments, a thermal collection layer can be formed on a surface of a flip chip die. The thermal collection layer can be configured... http://www.freshpatents.com/-dt20130516ptan20130119534.php Mon, 20 May 2013 13:35:02 -0700 A topographical feature is formed proximate to a conductive bond pad that is used to couple a solder bump to a semiconductor die. The topographical feature is separated from the conductive bond pad by a gap. In one embodiment, the topographical feature is formed at a location that is slightly... http://www.freshpatents.com/-dt20130516ptan20130119536.php Mon, 20 May 2013 13:35:02 -0700 A method and a combination of studs, silicon chips, and solder bumps configured to restrict motion of a plurality of silicon chips. The combination includes: a plurality of studs, a plurality of silicon chips, a plurality of target solder bumps, where the plurality of solder bumps are melted between the... http://www.freshpatents.com/-dt20130516ptan20130119533.php Mon, 20 May 2013 13:35:02 -0700 A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step... http://www.freshpatents.com/-dt20130516ptan20130119537.php Mon, 20 May 2013 13:35:02 -0700 A semiconductor device includes a wiring board, a semiconductor chip mounted on the wiring board, the semiconductor chip including a bump formation surface, a plurality of first bumps provided within a first region of the bump formation surface, the first bumps being arranged in a first area density, a plurality... http://www.freshpatents.com/-dt20130516ptan20130119542.php Mon, 20 May 2013 13:35:02 -0700 A multi-chip package has a substrate, and a plurality of memory dies stacked on the substrate. A plurality of buffer dies each has an input and an output. The input of a first buffer die is connectable to an external input. The output of a last buffer die of the... http://www.freshpatents.com/-dt20130516ptan20130119539.php Mon, 20 May 2013 13:35:02 -0700 A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A solder region is disposed in the polymer region and electrically coupled to the redistribution line. The solder region includes a second flat top surface not... http://www.freshpatents.com/-dt20130516ptan20130119541.php Mon, 20 May 2013 13:35:02 -0700 In a printed wiring board of a printed circuit board, a region for mounting a first semiconductor package is divided into a first region on which first solder ball electrodes are disposed and a second region on which first solder ball electrodes are not disposed, and a region for mounting... http://www.freshpatents.com/-dt20130516ptan20130119540.php Mon, 20 May 2013 13:35:02 -0700 Disclosed herein are a semiconductor package and a method for manufacturing the same. The method includes preparing a substrate having one surface and the other surface; mounting a semiconductor device mounted on one surface of the substrate; forming external connection terminals on the other surface of the substrate; forming a... http://www.freshpatents.com/-dt20130516ptan20130119538.php Mon, 20 May 2013 13:35:02 -0700 A method of making a wafer level chip size package (WCSP) comprising providing a die having a first face with a plurality of bond pads thereon, a second face opposite the first face and a plurality of side faces extending between the first face and the second face, at least... http://www.freshpatents.com/-dt20130516ptan20130119544.php Mon, 20 May 2013 13:35:02 -0700 A microelectronic package includes a substrate (110), a die (120) embedded within the substrate, the die having a front side (121) and a back side (122) and a through-silicon-via (123) therein, build-up layers (130) built up over the front side of the die, and a power plane (140) in physical... http://www.freshpatents.com/-dt20130516ptan20130119543.php Mon, 20 May 2013 13:35:02 -0700 Stacked wafer connections are enhanced by forming a though silicon via including a first via portion formed in an upper portion of a via hole and a second via portion in a lower portion of the via hole. Embodiments include forming a via hole in a first surface of a... http://www.freshpatents.com/-dt20130516ptan20130119547.php Mon, 20 May 2013 13:35:02 -0700 An integrated circuit device includes a substrate through which a first through-hole extends, and an interlayer insulating film on the substrate, the interlayer insulating film having a second through-hole communicating with the first through-hole. A Through-Silicon Via (TSV) structure is provided in the first through-hole and the second through-hole. The... http://www.freshpatents.com/-dt20130516ptan20130119546.php Mon, 20 May 2013 13:35:02 -0700 The method of the present invention comprises forming a word line crossing with an active region on a semiconductor substrate; forming a diffusion layer region; forming a first insulating film as high as a bit line to be formed; etching the first insulating film, while using, as a mask, a... http://www.freshpatents.com/-dt20130516ptan20130119545.php Mon, 20 May 2013 13:35:02 -0700 A semiconductor device and a method for forming the same are disclosed, which can protect a polysilicon layer of a bit line contact plug even when a critical dimension (CD) of the bit line is reduced by a fabrication change, thereby preventing defective resistivity caused by a damaged bit line... http://www.freshpatents.com/-dt20130516ptan20130119548.php Mon, 20 May 2013 13:35:02 -0700 Techniques for fabricating carbon nanotube-based devices are provided. In one aspect, a method for fabricating a carbon nanotube-based integrated circuit is provided. The method comprises the following steps. A first wafer comprising carbon nanotubes is provided. A second wafer comprising one or more device elements is provided. One or more... http://www.freshpatents.com/-dt20130516ptan20130119549.php Mon, 20 May 2013 13:35:02 -0700 A method includes placing a mold chase over a bottom package, wherein the bottom package has a connector at a top surface of the bottom package. The mold chase includes a cover, and a pin under and connected to the cover. The pin occupies a space extending from a top... http://www.freshpatents.com/-dt20130516ptan20130119550.php Mon, 20 May 2013 13:35:02 -0700 In one embodiment, a method of manufacturing a semiconductor device includes sequentially forming a first insulator, a second insulator, and a sacrificial layer on a semiconductor substrate, and forming plural core materials from the sacrificial layer and the second insulator. The method further includes forming first and second interconnects on... http://www.freshpatents.com/-dt20130516ptan20130119551.php Mon, 20 May 2013 13:35:02 -0700 A semiconductor element includes: a transparent substrate; a stack structure formed on the transparent substrate and having a metal oxide layer partially exposed through sidewalls of the stack structure; a plurality of leads spacingly formed on the stack structure and extending to the sidewalls of the stack structure; an insulating... http://www.freshpatents.com/-dt20130516ptan20130119556.php Mon, 20 May 2013 13:35:02 -0700 A chip package includes: a substrate having a first surface, a second surface, and a side surface connecting the first and the second surfaces; a dielectric layer located on the first surface; conducting pads comprising a first and a second conducting pads located in the dielectric layer; openings extending from... http://www.freshpatents.com/-dt20130516ptan20130119552.php Mon, 20 May 2013 13:35:02 -0700 A device includes a bottom chip and an active top die bonded to the bottom chip. A dummy die is attached to the bottom chip. The dummy die is electrically insulated from the bottom chip.... http://www.freshpatents.com/-dt20130516ptan20130119560.php Mon, 20 May 2013 13:35:02 -0700 A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach... http://www.freshpatents.com/-dt20130516ptan20130119559.php Mon, 20 May 2013 13:35:02 -0700 A semiconductor device has a first semiconductor die and first encapsulant deposited around the first semiconductor die. A first insulating layer is formed over the first semiconductor die and first encapsulant. A first conductive layer is formed over the first insulating layer and electrically connected to a contact pad of... http://www.freshpatents.com/-dt20130516ptan20130119554.php Mon, 20 May 2013 13:35:02 -0700 There is provided a semiconductor device comprising, a first metal pattern formed at a first metal level and extending in a first direction, a second metal pattern formed at the first metal level, extending in a second direction that is different than the first direction, and disposed on a side... http://www.freshpatents.com/-dt20130516ptan20130119553.php Mon, 20 May 2013 13:35:02 -0700 Disclosed herein is a semiconductor package including an electrical device having a first lateral surface; and a core substrate including a cavity in which the electrical device is positioned, wherein the core substrate is inclined in a thickness direction of the core substrate and has a second lateral surface that... http://www.freshpatents.com/-dt20130516ptan20130119558.php Mon, 20 May 2013 13:35:02 -0700 Provided is a stacked semiconductor package. The stacked semiconductor package of the present invention comprises: a substrate unit, which includes a connection substrate electrically connecting a first substrate having a contact pad and a second substrate having a contact pad; a first chip laminate at which a plurality of first... http://www.freshpatents.com/-dt20130516ptan20130119557.php Mon, 20 May 2013 13:35:02 -0700 Two systems including: a first system including a first die connected to a second die; and a second system including a third die connected to a fourth die; wherein the connected includes at least one through silicon via (TSV), and wherein the first die is substantially the same as the... http://www.freshpatents.com/-dt20130516ptan20130119555.php Mon, 20 May 2013 13:35:02 -0700 The present invention generally relates to the use of glass as the interposer material with the surface of the interposer and/or the walls of through vias in being coated by a stress relief barrier that provides thermal expansion and contraction stress relief and better metallization capabilities. The present invention discloses... http://www.freshpatents.com/-dt20130516ptan20130119561.php Mon, 20 May 2013 13:35:02 -0700 To provide a semiconductor device in which wireless communication is performed between devices formed over different substrates and connection defects of wirings are reduced. A first device having a first antenna is provided over a first substrate, a second device having a second antenna which can communicate with the first... http://www.freshpatents.com/-dt20130516ptan20130119562.php Mon, 20 May 2013 13:35:02 -0700 A semiconductor package includes a semiconductor chip, a first insulating layer formed to cover the semiconductor chip, a wiring structure formed on the first insulating layer. The wiring structure has an alternately layered configuration including wiring layers electrically connected to the semiconductor chip and interlayer insulating layers each located between... http://www.freshpatents.com/-dt20130516ptan20130119563.php Mon, 20 May 2013 13:35:02 -0700 An anisotropic conductive film composition for bonding a semiconductor device, the composition including: a binder system including a urethane resin having a glass transition temperature of about 100° C. or higher, a radical polymerizable compound, an organic peroxide, and conductive particles.... http://www.freshpatents.com/-dt20130516ptan20130119564.php Mon, 20 May 2013 13:35:02 -0700 wherein R1 and R2 are independently hydrogen or alkyl having 1 to 4 carbon atoms and two or more R1s or two or more R2s are the same or different; a is integer of 0 to 4; b is integer of 0 to 4; c is integer of 0 to... http://www.freshpatents.com/-dt20130516ptan20130119565.php Mon, 20 May 2013 13:35:02 -0700 A system for and a method of curing a material is provided. A material, such as an underfill material, is rotated during a curing process. The curing system may include a chamber, a holder to support one or more workpieces, and a rotating mechanism. The rotating mechanism rotates the workpieces... http://www.freshpatents.com/-dt20130516ptan20130119566.php Mon, 20 May 2013 13:35:02 -0700 The invention is related to a semiconductor chip, at-least also accomplished in a semiconductor installation, containing at-least also a long, relatively narrow semiconductor substrate transfer/processing tunnel-arrangement, wherein during its operation at-least also the taking place of successive semiconductor processings of the successive, typically uninterruptedly displacing semiconductor substrate-sections there through and...