http://www.freshpatents.com/Active-solid-state-devices--e-g--transistors-solid-state-diodes--dtnewntc257.php USPTO Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes) en-us Wed, 30 Apr 2008 12:27:09 -0700 1000 Wednesday Thursday Friday Saturday Sunday 141 31 http://www.freshpatents.com/index.php?rss=true http://www.freshpatents.com/images/freshpatentsnav_rss.gif http://www.freshpatents.com/Phase-change-memory-device-and-method-of-forming-the-same-dt20080424ptan20080093590.php Wed, 30 Apr 2008 12:27:09 -0700 Provided are a phase change memory device and a method of forming the same. According to the phase change memory, a first plug electrode and a second plug electrode are spaced apart from each other in a mold insulating layer. A phase change pattern is disposed on the mold insulating... http://www.freshpatents.com/Phase-change-memory-and-method-of-manufacturing-the-same-dt20080424ptan20080093592.php Wed, 30 Apr 2008 12:27:09 -0700 A structure of a phase-change memory which enables low-current rewrite and a method of manufacturing the same are provided. The phase-change memory comprises: an interlayer insulating film and a plug formed over a main surface of a silicon substrate; a phase-change film formed over the plug; and an upper electrode... http://www.freshpatents.com/Storage-nodes-phase-change-memory-devices-and-methods-of-manufacturing-the-same-dt20080424ptan20080093591.php Wed, 30 Apr 2008 12:27:09 -0700 A storage node may include a bottom electrode contact layer, a phase change layer connected to the bottom electrode contact layer, and a top electrode layer connected to the phase change layer. The bottom electrode contact layer may protrude toward the phase change layer. A phase change memory device may... http://www.freshpatents.com/Semiconductor-light-emitting-device-dt20080424ptan20080093593.php Wed, 30 Apr 2008 12:27:09 -0700 A semiconductor light emitting device may include an n-type contact layer on a substrate. An active layer may be on the n-type contact layer and/or include two or more quantum well layers and two or more barrier layers. A p-type contact layer may be on the active layer. Energy band... http://www.freshpatents.com/Thin-film-transistor-for-cross-point-memory-and-method-of-manufacturing-the-same-dt20080424ptan20080093595.php Wed, 30 Apr 2008 12:27:09 -0700 A thin film transistor used as a selection transistor for a three-dimensional stacking cross point memory and a method of manufacturing the thin film transistor are provided. The thin film transistor includes a substrate, a gate, a gate insulation layer, a channel, a source and a drain. The gate may... http://www.freshpatents.com/Semiconductor-device-dt20080424ptan20080093597.php Wed, 30 Apr 2008 12:27:09 -0700 A semiconductor device is provided in which function modes thereof can be changed without difficulty and failure analysis can be conducted in an apparatus in which the semiconductor device is mounted. A semiconductor device uses a ball grid array package and includes: a semiconductor chip that is provided within the... http://www.freshpatents.com/Semiconductor-device-and-method-of-fabricating-the-same-dt20080424ptan20080093596.php Wed, 30 Apr 2008 12:27:09 -0700 A semiconductor device includes a wiring layer that is formed on a substrate and includes a first pad contact region and a second pad contact region, a passivation layer that includes a first opening and a second opening on the wiring layer and a protrusion pattern dividing the first opening... http://www.freshpatents.com/Image-display-unit-and-method-for-manufacutre-the-same-dt20080424ptan20080093602.php Wed, 30 Apr 2008 12:27:09 -0700 The present invention provides an image display unit, which can be manufactured in shorter time by designing a thin-film transistor, by which it is possible to reduce the number of processes of ion implantation and photolithographic processes. A gate electrode GT is designed in a laminated structure of a thin... http://www.freshpatents.com/Light-emitting-chip-package-and-manufacturing-method-thereof-dt20080424ptan20080093606.php Wed, 30 Apr 2008 12:27:09 -0700 A method for manufacturing a light emitting chip package includes bonding a patterned metal plate having at least a thermal enhanced plate and many contacts around the same to a substrate and bonding a film-like circuit layer to the patterned metal plate. Many conductive wires are formed to connect the... http://www.freshpatents.com/Light-emitting-diode-device-method-of-fabrication-and-use-thereof-dt20080424ptan20080093607.php Wed, 30 Apr 2008 12:27:09 -0700 A light emitting diode device which, in use, has its light emitting region occupying a plane substantially perpendicular to a plane occupied by the surface on which the device is mounted. The primary light emission directions of the light emitting region are parallel to the surface on which the device... http://www.freshpatents.com/Semiconductor-light-emitting-device-dt20080424ptan20080093612.php Wed, 30 Apr 2008 12:27:09 -0700 A plurality of semiconductor layers including an active layer 6 and a light extract layer 4, and a reflective metal film 11 are formed in a semiconductor light emitting device. The light extract layer 4 is formed of a plurality of layers 23, 24 having different composition ratios. An irregularity... http://www.freshpatents.com/Imager-device-with-electric-connections-to-electrical-device-dt20080424ptan20080093613.php Wed, 30 Apr 2008 12:27:09 -0700 An imager device is disclosed including a first substrate having an array of photo-sensitive elements formed thereon, a first conductive layer formed above the first substrate, a first conductive member extending through the first substrate, the first conductive member being conductively coupled to the first conductive layer, a standoff structure... http://www.freshpatents.com/Method-for-obtaining-a-better-color-rendering-with-a-photoluminescence-plate-dt20080424ptan20080093615.php Wed, 30 Apr 2008 12:27:09 -0700 The present invention is a method for obtaining a better color rendering with a photoluminescence plate, and the better color rendering is obtained by using UV radiating on the photoluminescence plate stacked with a red photoluminescence plate, a green photoluminescence plate and a blue photoluminescence plate. Therefore, the color rendering... http://www.freshpatents.com/Multiple-reflection-layer-electrode-compound-semiconductor-light-emitting-device-having-the-same-and-methods-of-fabricating-the-same-dt20080424ptan20080093617.php Wed, 30 Apr 2008 12:27:09 -0700 Provided are a multiple reflection layer electrode, a compound semiconductor light emitting device having the same and methods of fabricating the same. The multiple reflection layer electrode may include a reflection layer on a p-type semiconductor layer, an APL (agglomeration protecting layer) on the reflection layer so as to prevent... http://www.freshpatents.com/Semiconductor-light-emitting-device-dt20080424ptan20080093619.php Wed, 30 Apr 2008 12:27:09 -0700 A first conductivity type cladding layer 2, a first side multilayer 9, an active layer 4, a second side multilayer 10, and a second conductivity type cladding layer 3 are provided in a semiconductor light emitting device. The first side multilayer 9 is provided between the first conductivity type cladding... http://www.freshpatents.com/Vertical-light-emitting-diode-and-method-of-manufacturing-the-same-dt20080424ptan20080093618.php Wed, 30 Apr 2008 12:27:09 -0700 Provided is a vertical LED including an n-electrode; an n-type GaN layer formed under the n-electrode, the n-type GaN layer having a surface coming in contact with the n-electrode, the surface having a Ga+N layer containing a larger amount of Ga than that of N; an active layer formed under... http://www.freshpatents.com/Led-package-and-manufacturing-method-thereof-dt20080424ptan20080093620.php Wed, 30 Apr 2008 12:27:09 -0700 A light emitting diode (LED) package including a carrier, an adhering layer and an LED chip is provided. The adhering layer is disposed on the carrier. The LED chip is disposed on the adhering layer and electrically connected to the carrier. The material of the adhering layer comprises a lead-free... http://www.freshpatents.com/Resistance-variable-devices-with-controllable-channels-dt20080424ptan20080093589.php Wed, 30 Apr 2008 12:27:09 -0700 A memory element having a first electrode is provided, wherein the first electrode comprises at least one conductive nanostructure. The memory element further includes a second electrode and a resistance variable material layer between the first and second electrodes. The first electrode electrically is coupled to the resistance variable material.... http://www.freshpatents.com/Organic-semiconductor-device-manufacturing-method-of-the-same-organic-transistor-array-and-display-dt20080424ptan20080093594.php Wed, 30 Apr 2008 12:27:09 -0700 The present invention mainly intends to provide an organic semiconductor device having an organic semiconductor transistor reduced in off current. In order to achieve the object, the present invention provides an organic semiconductor device comprising a substrate and an organic semiconductor transistor provided with a gate electrode formed on the... http://www.freshpatents.com/Array-substrate-with-reduced-pixel-defect-method-of-manufacturing-the-same-and-liquid-crystal-display-panel-having-the-same-dt20080424ptan20080093599.php Wed, 30 Apr 2008 12:27:09 -0700 An array substrate includes a transparent substrate, a switching element, an insulating layer and a pixel electrode. The switching element includes a gate electrode formed on the transparent substrate and connected to a gate line, a channel layer formed on the gate electrode and extended in a first direction, a... http://www.freshpatents.com/Substrate-for-display-device-manufacturing-method-for-same-and-display-device-dt20080424ptan20080093598.php Wed, 30 Apr 2008 12:27:09 -0700 The present invention provides the substrate for a display device, comprising a scan line, a signal line and a switching element on an insulating substrate, and further comprising an interlayer insulation film and a pixel electrode, the switching element is provided at an intersection of the scan line and the... http://www.freshpatents.com/Thin-film-transistor-array-panel-and-manufacturing-method-thereof-dt20080424ptan20080093600.php Wed, 30 Apr 2008 12:27:09 -0700 A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer;... http://www.freshpatents.com/Integrated-circuit-devices-including-a-transcription-preventing-pattern-and-methods-of-manufacturing-the-same-dt20080424ptan20080093601.php Wed, 30 Apr 2008 12:27:09 -0700 Integrated circuit devices are provided including a first single-crystalline layer and an insulating layer pattern on the first single-crystalline layer. The insulating layer pattern has an opening therein that partially exposes the first single-crystalline layer. A seed layer is in the opening. A second single-crystalline layer is on the insulating... http://www.freshpatents.com/Lower-substrate-display-apparatus-having-the-same-and-method-of-manufacturing-the-same-dt20080424ptan20080093603.php Wed, 30 Apr 2008 12:27:09 -0700 In a lower substrate, a display apparatus having the lower substrate and a method of manufacturing the lower substrate, the lower substrate includes a pixel area and a circuit area. An image is displayed in the pixel area. A first signal electrode is disposed in a circuit area. A first... http://www.freshpatents.com/Pixel-structure-dt20080424ptan20080093604.php Wed, 30 Apr 2008 12:27:09 -0700 A memory cell suitable for being disposed over a substrate is provided. The memory cell includes a poly-silicon island, a first dielectric layer, a trapping layer, a second dielectric layer and a control gate. The poly-silicon island is disposed on the substrate and includes a source region, a drain region... http://www.freshpatents.com/Method-for-monolithically-integrating-silicon-carbide-microelectromechanical-devices-with-electronic-circuitry-dt20080424ptan20080093605.php Wed, 30 Apr 2008 12:27:09 -0700 A device and method of forming electronics and microelectromechanical on a silicon carbide substrate having a slow etch rate is performed by forming circuitry on the substrate. A protective layer is formed over the circuitry having a slower etch rate than the etch rate of the silicon carbide substrate. Microelectromechanical... http://www.freshpatents.com/Engineered-structure-for-solid-state-light-emitters-dt20080424ptan20080093608.php Wed, 30 Apr 2008 12:27:09 -0700 An engineered structure of a light emitting device comprises multiple layers of alternating active and buffer materials disposed between AC or DC electrodes, which generate an electric field. The active layers comprise luminescent centers, e.g. group IV semiconductor nanocrystals, in a host matrix, e.g. a wide bandgap semiconductor or dielectric... http://www.freshpatents.com/Nitride-semiconductor-light-emitting-device-and-fabrication-method-thereof-dt20080424ptan20080093610.php Wed, 30 Apr 2008 12:27:09 -0700 A nitride semiconductor light emitting device comprises a first nitride semiconductor layer, an active layer of a single or multiple quantum well structure formed on the first nitride semiconductor layer and including an InGaN well layer and a multilayer barrier layer, and a second nitride semiconductor layer formed on the... http://www.freshpatents.com/Silicon-nitride-layer-for-light-emitting-device-light-emitting-device-using-the-same-and-method-of-forming-silicon-nitride-layer-for-light-emitting-device-dt20080424ptan20080093609.php Wed, 30 Apr 2008 12:27:09 -0700 Provided are a silicon nitride layer for a light emitting device, light emitting device using the same, and method of forming the silicon nitride layer for the light emitting device. The silicon nitride layer of the light emitting device includes a silicon nitride matrix and silicon nanocrystals formed in the... http://www.freshpatents.com/Method-for-production-of-a-radiation-emitting-semiconductor-chip-dt20080424ptan20080093611.php Wed, 30 Apr 2008 12:27:09 -0700 A method for micropatterning a radiation-emitting surface of a semiconductor layer sequence for a thin-film light-emitting diode chip. The semiconductor layer sequence is grown on a substrate. A mirror layer is formed or applied on the semiconductor layer sequence, which reflects back into the semiconductor layer sequence at least part... http://www.freshpatents.com/Light-emitting-diode-illumination-source-dt20080424ptan20080093616.php Wed, 30 Apr 2008 12:27:09 -0700 The invention provides light emitting diode illumination source having excellent properties as an illumination source such as a flat spectral distribution in the wavelength region from green to red and a sufficient emission intensity in the red region, comprising a light emitting diode having multiple peaks with a half-value width... http://www.freshpatents.com/Semiconductor-light-emitting-device-lighting-module-illumination-apparatus-surface-mount-led-and-bullet-led-dt20080424ptan20080093614.php Wed, 30 Apr 2008 12:27:09 -0700 Disclosed is a semiconductor light emitting device (10) that includes an LED chip (14) mounted on a base substrate (12) and a phosphor (16) covering the LED chip (14). The LED chip (14) is substantially in the shape of a regular hexagonal prism and the phosphor (16) is substantially in... http://www.freshpatents.com/Light-emitter-based-devices-with-lattice-mismatched-semiconductor-structures-dt20080424ptan20080093622.php Wed, 30 Apr 2008 12:27:09 -0700 Some aspects for the invention include a method and a structure including a light-emitting device disposed over a second crystalline semiconductor material formed over a semiconductor substrate comprising a first crystalline material.... http://www.freshpatents.com/N-type-group-iii-nitride-semiconductor-layer-stacked-structure-dt20080424ptan20080093621.php Wed, 30 Apr 2008 12:27:09 -0700 An object of the present invention provides an n-type Group III nitride semiconductor stacked layer structure of a low resistance having excellent flatness generating few cracks and pits in the uppermost surface. The inventive n-type Group III nitride semiconductor stacked layer structure comprises a first n-type layer which includes a... http://www.freshpatents.com/Insulated-gate-semiconductor-device-and-method-for-manufacturing-same-dt20080424ptan20080093623.php Wed, 30 Apr 2008 12:27:09 -0700 In an insulated gate semiconductor device (1) having an N− type base region (11), P+ type collector regions (12), P type base regions (13), and N+type emitter regions (14), an N+ type collector-short region (15) which extends toward the N− type base region (11) farther than the P+ type collector... http://www.freshpatents.com/Integrated-circuit-esd-protection-dt20080424ptan20080093624.php Wed, 30 Apr 2008 12:27:09 -0700 A protective device in a semiconductor may comprise a substrate of a first conductivity type, an epitaxial layer formed on top of the substrate, a body area formed within the epitaxial layer of a second conductivity type extending from a top surface into the epitaxial layer, a first area of... http://www.freshpatents.com/Photoconductive-device-dt20080424ptan20080093625.php Wed, 30 Apr 2008 12:27:09 -0700 A semiconductor structure includes a GaAs or InP substrate, an InxGa1-xAs epitaxial layer grown on the substrate, where x is greater than about 0.01 and less than about 0.53, and a wider bandgap epitaxial layer grown as a cap layer on top of the InxGa1-xAs epitaxial layer.... http://www.freshpatents.com/Metal-oxide-field-effect-transistor-with-a-sharp-halo-dt20080424ptan20080093629.php Wed, 30 Apr 2008 12:27:09 -0700 Disclosed are embodiments of a MOSFET with defined halos that are bound to defined source/drain extensions and a method of forming the MOSFET. A semiconductor layer is etched to form recesses that undercut a gate dielectric layer. A low energy implant forms halos. Then, a COR pre-clean is performed and... http://www.freshpatents.com/Methods-of-forming-semiconductor-devices-having-multiple-channel-mos-transistors-and-related-intermediate-structures-dt20080424ptan20080093628.php Wed, 30 Apr 2008 12:27:09 -0700 In a method of manufacturing a semiconductor device, a preliminary active pattern including gate layers and channel layers is formed on a substrate. The gate layers and the channel layers are alternatively stacked. A hard mask is formed on the preliminary active pattern. The preliminary active pattern is partially etched... http://www.freshpatents.com/Nitride-semiconductor-device-dt20080424ptan20080093626.php Wed, 30 Apr 2008 12:27:09 -0700 A nitride semiconductor device includes: a first nitride semiconductor layer formed of non-doped AlxGa1-XN (0≦X<1); a second nitride semiconductor layer formed on the first nitride semiconductor layer of non-doped or n-type AlYGa1-YN (0<Y≦1, X<Y), and having a smaller lattice constant than that of the first nitride semiconductor layer; a third... http://www.freshpatents.com/Semiconductor-mos-transistor-device-and-method-for-making-the-same-dt20080424ptan20080093627.php Wed, 30 Apr 2008 12:27:09 -0700 A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the... http://www.freshpatents.com/Heterostructure-field-effect-transistor-dt20080424ptan20080093630.php Wed, 30 Apr 2008 12:27:09 -0700 A HEMT has a substrate (2), buffer layer (4), channel layer (8), spacer layer (10), delta doped layer (12), Schottky barrier layer (14) and cap layer (18) and metal layer (20), the latter forming a Schottky barrier with the underlying semiconductor. The channel may be of GaInAs and the barrier... http://www.freshpatents.com/Contact-structure-for-semiconductor-devices-dt20080424ptan20080093631.php Wed, 30 Apr 2008 12:27:09 -0700 A semiconductor device has a substrate of one type of semiconductor material, such as silicon. A contact structure is formed on the substrate, and the contact structure is formed of a compound of a metal and a second type of semiconductor material, such as germanium. The contact structure according to... http://www.freshpatents.com/Size-reduced-layout-of-cell-based-integrated-circuit-with-power-switch-dt20080424ptan20080093632.php Wed, 30 Apr 2008 12:27:09 -0700 An integrated circuit is provided with a first power line, a plurality of additional power lines intersecting with the first power line, a plurality of power switch transistors each having a drain connected with the first power line and a source connected with one of the additional power lines, a... http://www.freshpatents.com/Complementary-metal-oxide-semiconductor--cmos--image-sensor-and-fabricating-method-thereof-dt20080424ptan20080093633.php Wed, 30 Apr 2008 12:27:09 -0700 A complementary metal-oxide-semiconductor (CMOS) image sensor including a substrate, a p type well, a light emitting diode, a p type gate structure and a plurality of n type gate structures is provided. The substrate has a photo sensitive region and a transistor device region, and the p type well is... http://www.freshpatents.com/Silicon-on-insulator-based-radiation-detection-device-and-method-dt20080424ptan20080093634.php Wed, 30 Apr 2008 12:27:09 -0700 Structures and a method for detecting ionizing radiation using silicon-on-insulator (SOI) technology are disclosed. In one embodiment, the invention includes a substrate having a buried insulator layer formed over the substrate and an active layer formed over the buried insulator layer. Active layer may be fully depleted. A transistor is... http://www.freshpatents.com/Junction-fet-and-method-of-manufacturing-the-same-dt20080424ptan20080093635.php Wed, 30 Apr 2008 12:27:09 -0700 A shallow channel region is selectively formed by ion implantation and diffusion. Since the channel region forms pn junctions with a p type semiconductor layer having a relatively low impurity concentration, a reduction of a junction capacitance leads to improvement in high-frequency characteristics. Moreover, since a gate region can also... http://www.freshpatents.com/Scalable-process-and-structure-for-jfet-for-small-and-decreasing-line-widths-dt20080424ptan20080093636.php Wed, 30 Apr 2008 12:27:09 -0700 A scalable device structure and process for forming a normally off JFET with 45 NM linewidths or less. The contacts to the source, drain and gate areas are formed by forming a layer of oxide of a thickness of less than 1000 angstroms, and, preferably 500 angstroms or less on... http://www.freshpatents.com/Vertical-junction-field-effect-transistor-with-mesa-termination-and-method-of-making-the-same-dt20080424ptan20080093637.php Wed, 30 Apr 2008 12:27:09 -0700 A vertical junction field effect transistor (VJFET) having a mesa termination and a method of making the device are described. The device includes: an n-type mesa on an n-type substrate; a plurality of raised n-type regions on the mesa comprising an upper n-type layer on a lower n-type layer; p-type... http://www.freshpatents.com/Semiconductor-device-dt20080424ptan20080093638.php Wed, 30 Apr 2008 12:27:09 -0700 In a J-FET for large current use, there has been a limitation on reduction in a chip size or enlargement of the operation regions because two operation regions are arranged in line along a diagonal line of a chip. To eliminate the limitation, in this invention, gate regions are extended... http://www.freshpatents.com/Method-for-forming-gate-insulating-layer-of-mos-transistor-dt20080424ptan20080093639.php Wed, 30 Apr 2008 12:27:09 -0700 A method for forming a gate insulating layer of a Metal Oxide Semiconductor (MOS) transistor includes forming an oxide layer on a semiconductor substrate, implanting plasma nitrogen ions into the oxide layer, and performing heat treatment on the nitrogen ion-implanted oxide layer to eliminate damage to a surface of the... http://www.freshpatents.com/Method-for-tuning-epitaxial-growth-by-interfacial-doping-and-structure-including-same-dt20080424ptan20080093640.php Wed, 30 Apr 2008 12:27:09 -0700 A method that allows for uniform, simultaneous epitaxial growth of a semiconductor material on dissimilarly doped semiconductor surfaces (n-type and p-type) that does not impart substrate thinning via a novel surface preparation scheme, as well as a structure that results from the implementation of this scheme into the process integration... http://www.freshpatents.com/Method-of-manufacturing-a-multi-path-lateral-high-voltage-field-effect-transistor-dt20080424ptan20080093641.php Wed, 30 Apr 2008 12:27:09 -0700 High-Voltage Lateral MOSFET and Lateral Double-diffused MOS (LDMOS) for HV power applications with multiple paths for conduction in the drain extension and methods of fabrication are described.... http://www.freshpatents.com/Image-sensor-and-fabricating-method-thereof-dt20080424ptan20080093642.php Wed, 30 Apr 2008 12:27:09 -0700 Embodiments relate to an image sensor having a gate spacer and a fabricating method by which damage in a photodiode area can be prevented. Embodiments relate to a method of fabricating an image sensor including forming a gate electrode over a substrate having a prescribed photodiode area. A first oxide... http://www.freshpatents.com/Non-volatile-memory-device-and-fabrication-method-dt20080424ptan20080093643.php Wed, 30 Apr 2008 12:27:09 -0700 Provided is a non-volatile memory device capable of operating with two cells at each one unit. The memory cell unit includes a common source region on an active region, a select gate covering the common source region, a first memory gate on the active region adjacent to one side of... http://www.freshpatents.com/Dram-arrays-vertical-transistor-structures-and-methods-of-forming-transistor-structures-and-dram-arrays-dt20080424ptan20080093644.php Wed, 30 Apr 2008 12:27:09 -0700 The invention includes a method of forming a semiconductor construction. Dopant is implanted into the upper surface of a monocrystalline silicon substrate. The substrate is etched to form a plurality of trenches and cross-trenches which define a plurality of pillars. After the etching, dopant is implanted within the trenches to... http://www.freshpatents.com/Fabrication-process-for-increased-capacitance-in-an-embedded-dram-memory-dt20080424ptan20080093645.php Wed, 30 Apr 2008 12:27:09 -0700 An embedded memory system includes an array of dynamic random access memory (DRAM) cells, which are isolated with deep trench isolation, and logic transistors, which are isolated with shallow trench isolation. Each DRAM cell includes an access transistor and a capacitor structure. The capacitor structure is fabricated by forming a... http://www.freshpatents.com/Non-volatile-memory-device-and-method-for-fabricating-the-same-dt20080424ptan20080093646.php Wed, 30 Apr 2008 12:27:09 -0700 A non-volatile memory device comprises a semiconductor substrate having source/drain regions formed at both ends of a channel region, a gate structure forming an offset region by being separated a predetermined distance from the source region and comprising a charge accumulation region and a control gate sequentially deposited in the... http://www.freshpatents.com/Split-gate-non-volatile-memory-devices-and-methods-of-forming-the-same-dt20080424ptan20080093647.php Wed, 30 Apr 2008 12:27:09 -0700 Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.... http://www.freshpatents.com/Flash-memory-devices-and-methods-for-fabricating-flash-memory-devices-dt20080424ptan20080093651.php Wed, 30 Apr 2008 12:27:09 -0700 A flash memory device includes a cell string having a plurality of cell transistors connected in series, and a string selection transistor and a ground selection transistor connected to both ends of the cell string, respectively, wherein the cell transistor has a channel impurity concentration higher than a channel impurity... http://www.freshpatents.com/Non-volatile-memory-device-and-methods-of-manufacturing-and-operating-the-same-dt20080424ptan20080093649.php Wed, 30 Apr 2008 12:27:09 -0700 A non-volatile memory device and methods of manufacturing and operating the same are provided. In a method of manufacturing a non-volatile memory device, a substrate having a stepped portion that may include a first horizontal face, a second horizontal face lower than the first horizontal face, and a vertical face... http://www.freshpatents.com/Non-volatile-memory-devices-including-double-diffused-junction-regions-and-methods-of-fabricating-the-same-dt20080424ptan20080093648.php Wed, 30 Apr 2008 12:27:09 -0700 A nonvolatile memory device includes a string selection gate and a ground selection gate on a semiconductor substrate, and a plurality of memory cell gates on the substrate between the string selection gate and the ground selection gate. First impurity regions extend into the substrate to a first depth between... http://www.freshpatents.com/Nonvolatile-memory-device-and-method-of-forming-the-same-dt20080424ptan20080093650.php Wed, 30 Apr 2008 12:27:09 -0700 Provided is a nonvolatile memory device and a method of forming the nonvolatile memory device. The nonvolatile memory device includes a floating gate formed on a first active region doped with a first-conductivity-type dopant. The floating gate is doped with the first-conductivity-type dopant. Therefore, the thickness of a tunnel insulation... http://www.freshpatents.com/Semiconductor-device-and-method-of-manufacturing-same-dt20080424ptan20080093652.php Wed, 30 Apr 2008 12:27:09 -0700 A semiconductor device comprising: a transistor region formed on a semiconductor substrate and having a plurality of memory cell arrays formed of a plurality of memory cell transistors and select transistors one each of which is disposed on one and the other sides of said plurality of memory cell transistors;... http://www.freshpatents.com/Nonvolatile-memory-devices-and-methods-for-forming-same-dt20080424ptan20080093653.php Wed, 30 Apr 2008 12:27:09 -0700 Non-volatile memory devices include a substrate with first and second semiconductor active regions therein. These active regions are separated from each other by a trench isolation region, which has a recess therein that extends along its length. First and second floating gate electrodes are provided. These first and second floating... http://www.freshpatents.com/Non-volatile-two-transistor-programmable-logic-cell-and-array-layout-dt20080424ptan20080093654.php Wed, 30 Apr 2008 12:27:09 -0700 A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within... http://www.freshpatents.com/Semiconductor-device-and-method-for-forming-the-same-dt20080424ptan20080093655.php Wed, 30 Apr 2008 12:27:09 -0700 Provided are a semiconductor device and a method of forming the semiconductor device. The semiconductor substrate includes a cell region, a peripheral region, and a boundary region between the cell region and the peripheral region; a plurality of device isolation patterns defining the cell region, the peripheral region, and the... http://www.freshpatents.com/Semiconductor-devices-and-methods-of-fabricating-the-same-dt20080424ptan20080093656.php Wed, 30 Apr 2008 12:27:09 -0700 A semiconductor device includes a device isolation layer in a semiconductor substrate, an active region defined by the device isolation layer, the active region including a main surface and a recess region including a bottom surface that is lower than the main surface, and a gate electrode formed over the... http://www.freshpatents.com/Nonvolatile-memory-devices-and-methods-of-fabricating-the-same-dt20080424ptan20080093657.php Wed, 30 Apr 2008 12:27:09 -0700 A method of fabricating a nonvolatile memory device includes forming at least one insulating layer on at least one of a semiconductor substrate and a layer including a semi-conductive material, and performing a plasma process using fluorine on the semiconductor. In some cases, an interface between the insulating layer and... http://www.freshpatents.com/Method-for-nitriding-tunnel-oxide-film-method-for-manufacturing-non-volatile-memory-device-non-volatile-memory-device-control-program-and-computer-readable-recording-medium-dt20080424ptan20080093658.php Wed, 30 Apr 2008 12:27:09 -0700 When nitriding a tunnel oxide film in a nonvolatile memory device a nitrided region is formed in the surface portion of the tunnel oxide film by a plasma processing using a process gas containing nitrogen gas.... http://www.freshpatents.com/Electrically-programmable-resistor-and-methods-dt20080424ptan20080093659.php Wed, 30 Apr 2008 12:27:09 -0700 Methods of electrically programming a diffusion resistor by using trapped charge in a trapped charge region adjacent to the resistor to vary the resistance of the resistor, and the resistor, are disclosed. In one embodiment, a method includes forming a diffusion resistor in a substrate; forming a trapped charge region... http://www.freshpatents.com/Flash-memory-device-and-method-for-manufacturing-the-same-dt20080424ptan20080093660.php Wed, 30 Apr 2008 12:27:09 -0700 A flash memory device includes a semiconductor substrate, a gate insulating layer having a first width formed on the semiconductor substrate to trap carriers tunneled from the semiconductor substrate and a metal electrode on the gate insulating layer to receive a voltage required for tunneling. The metal electrode having a... http://www.freshpatents.com/Non-volatile-memory-device-having-a-charge-trapping-layer-and-method-for-fabricating-the-same-dt20080424ptan20080093661.php Wed, 30 Apr 2008 12:27:09 -0700 A non-volatile memory device comprises a substrate, a tunneling layer over the substrate, a charge trapping layer comprising a stoichiometric silicon nitride layer and a silicon-rich silicon nitride layer over the tunneling layer, a blocking layer over the charge trapping layer, and a control gate electrode over the blocking layer.... http://www.freshpatents.com/Nonvolatile-memory-device-and-method-for-forming-the-same-dt20080424ptan20080093663.php Wed, 30 Apr 2008 12:27:09 -0700 A method of forming a memory device includes forming a first insulating pattern and a polysilicon pattern in a peripheral region of a substrate, forming a cell gate insulating pattern including a second insulating pattern, a charge storage pattern, and a third insulating pattern in a cell region of the... http://www.freshpatents.com/Semiconductor-memory-device-including-recessed-control-gate-electrode-dt20080424ptan20080093662.php Wed, 30 Apr 2008 12:27:09 -0700 A semiconductor memory device may include a semiconductor substrate, at least one control gate electrode, at least one storage node layer, at least one tunneling insulating layer, at least one blocking insulating layer, and/or first and second channel regions. The at least one control gate electrode may be recessed into... http://www.freshpatents.com/Memory-device-and-method-of-manufacturing-the-same-dt20080424ptan20080093664.php Wed, 30 Apr 2008 12:27:09 -0700 In a memory device and a method of manufacturing the memory device, the memory device includes a first gate electrode enclosed by a first gate insulating layer, a second gate electrode enclosed by a second gate insulating layer that can be an ONO layer, and a channel region vertically extending... http://www.freshpatents.com/Semiconductor-apparatus-and-method-of-manufacturing-the-same-dt20080424ptan20080093665.php Wed, 30 Apr 2008 12:27:09 -0700 A vertical power MOSFET includes a semiconductor substrate including a trench, a gate electrode layer having a prescribed impurity concentration and being formed inside the trench, and a cap insulating layer having a lower impurity concentration than the impurity concentration of the gate electrode layer and covering the gate electrode... http://www.freshpatents.com/Semiconductor-device-and-manufacturing-method-thereof-dt20080424ptan20080093666.php Wed, 30 Apr 2008 12:27:09 -0700 A semiconductor device having a simple structure with selectively formed full-silicide (FUSI) and partial silicide gate electrodes and a manufacturing method thereof are provided. According to one aspect, there is provided a semiconductor device includes a first field effect transistor (MOSFET), and a second MOSFET, the first MOSFET including a... http://www.freshpatents.com/Metal-oxide-semiconductor-device-having-trenched-diffusion-region-and-method-of-forming-same-dt20080424ptan20080093667.php Wed, 30 Apr 2008 12:27:09 -0700 An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A... http://www.freshpatents.com/Semiconductor-device-and-method-of-manufacturing-the-same-dt20080424ptan20080093669.php Wed, 30 Apr 2008 12:27:09 -0700 The present invention aims at offering the semiconductor device which has the structure which are a high speed and a low power, and can be integrated highly. The present invention is a semiconductor device formed in the SOI substrate by which the BOX layer and the SOI layer were laminated... http://www.freshpatents.com/Method-for-the-manufacture-of-a-semiconductor-device-and-a-semiconductor-device-obtained-through-it-dt20080424ptan20080093668.php Wed, 30 Apr 2008 12:27:09 -0700 The invention relates to a semiconductor device (10) having a semiconductor body (2), comprising a field effect transistor, a first gate dielectric (6A) being formed on a first surface at the location of the channel region (5) and on it a first gate electrode (7), a sunken ion implantation (20)... http://www.freshpatents.com/Signal-and-or-ground-planes-with-double-buried-insulator-layers-and-fabrication-process-dt20080424ptan20080093670.php Wed, 30 Apr 2008 12:27:09 -0700 The present invention describes a method including the steps of providing a single crystal semiconductor substrate, forming a layer of rare earth silicide on a surface of the semiconductor substrate, forming a first layer of insulating material on the layer of rare earth silicide, forming a layer of electrically conductive... http://www.freshpatents.com/Semi-conductor-element-comprising-an-integrated-zener-diode-and-method-for-the-production-thereof-dt20080424ptan20080093671.php Wed, 30 Apr 2008 12:27:09 -0700 In order to protect a semiconductor component against overvoltages, the steps which are used for production of bipolar transistors and CMOS structures in the semiconductor component are used for integrated parallel production of a zener diode. This has a first and a second n-doped zone, which extend between the surface... http://www.freshpatents.com/String-contact-structure-for-high-voltage-esd-dt20080424ptan20080093672.php Wed, 30 Apr 2008 12:27:09 -0700 The present invention relates to an electrostatic discharge (ESD) protection scheme and particularly to a string contact structure for an improved ESD performance. In an embodiment, the invention provides a method for forming an ESD protection circuit for protecting an internal circuit from damage due to an ESD voltage appearing... http://www.freshpatents.com/Semiconductor-device-and-fabrication-method-thereof-dt20080424ptan20080093673.php Wed, 30 Apr 2008 12:27:09 -0700 A semiconductor device includes a first MIS transistor on a first active region of a semiconductor substrate, the first MIS transistor including: a first gate insulating film provided on the first active region; a first gate electrode provided on the first gate insulating film; a first stressor insulating film provided... http://www.freshpatents.com/Fin-field-effect-transistor-and-method-of-manufacturing-the-same-dt20080424ptan20080093674.php Wed, 30 Apr 2008 12:27:09 -0700 In a fin field effect transistor (FET), an active pattern protrudes in a vertical direction from a substrate and extends across the substrate in a first horizontal direction. A first silicon nitride pattern is formed on the active pattern, and a first oxide pattern and a second silicon nitride pattern... http://www.freshpatents.com/Mos-devices-with-continuous-contact-etch-stop-layer-dt20080424ptan20080093675.php Wed, 30 Apr 2008 12:27:09 -0700 A semiconductor structure includes a substrate, a gate stack on the substrate, a source/drain region adjacent the gate stack, a source/drain silicide region on the source/drain region, a protection layer on the source/drain silicide region, wherein a region over the gate stack is substantially free from the protection layer, and... http://www.freshpatents.com/Semiconductor-device-and-fabrication-method-thereof-dt20080424ptan20080093676.php Wed, 30 Apr 2008 12:27:09 -0700 A semiconductor device having a field effect transistor (FET) with enhanced performance by reduction of electrical contact resistance of electrodes and resistance of the electrodes per se is disclosed. The FET includes an n-type FET having a channel region formed in a semiconductor substrate, a gate electrode insulatively overlying the... http://www.freshpatents.com/Nand-type-non-volatile-memory-device-and-method-of-forming-the-same-dt20080424ptan20080093678.php Wed, 30 Apr 2008 12:27:09 -0700 A NAND type non-volatile memory device and a method for forming the same. Well bias lines are disposed substantially parallel to other wiring lines at equal intervals. Active regions that are electrically connected to the well bias line are disposed substantially parallel to other active regions at the same equal... http://www.freshpatents.com/Semiconductor-devices-and-methods-of-fabricating-the-same-dt20080424ptan20080093677.php Wed, 30 Apr 2008 12:27:09 -0700 Provided are semiconductor devices and methods of fabricating the same. A semiconductor device may include a semiconductor substrate with a device isolation layer defining HVE and HVD active regions. Gate insulation layer patterns may be disposed on the HVE and HVD active regions. Gate electrodes may be disposed on the... http://www.freshpatents.com/Semiconductor-device-dt20080424ptan20080093679.php Wed, 30 Apr 2008 12:27:09 -0700 At least part of an element isolation region, an interlayer insulating film, and a protection insulating film, other than a gate insulating film (silicon oxide film), is formed of carbon fluoride (CFx, 0.3<x<0.6) or hydrocarbon (CHy, 0.8<y<1.2).... http://www.freshpatents.com/Oxide-nitride-stack-gate-dielectric-dt20080424ptan20080093680.php Wed, 30 Apr 2008 12:27:09 -0700 A method of making a semiconductor structure comprises forming an oxide layer on a substrate; forming a silicon nitride layer on the oxide layer; annealing the layers in NO; and annealing the layers in ammonia. The equivalent oxide thickness of the oxide layer and the silicon nitride layer together is... http://www.freshpatents.com/Semiconductor-device-and-method-for-fabricating-the-same-dt20080424ptan20080093681.php Wed, 30 Apr 2008 12:27:09 -0700 A semiconductor device includes: a semiconductor substrate; an isolation region formed on a semiconductor substrate, the top surface of the isolation region being located above the top surface of the semiconductor substrate; a fully silicided gate line continuously formed to cover part of the top surface of an active region... http://www.freshpatents.com/Polysilicon-levels-for-silicided-structures-including-mosfet-gate-electrodes-and-3d-devices-dt20080424ptan20080093682.php Wed, 30 Apr 2008 12:27:09 -0700 Semiconductor structures having a silicided gate electrode and methods of manufacture are provided. A device comprises a first silicided structure formed in a first active region and a second silicided structure formed in a second active region. The two silicided structures have different metal concentrations. A method of forming a... http://www.freshpatents.com/Semiconductor-scheme-for-reduced-circuit-area-in-a-simplified-process-dt20080424ptan20080093683.php Wed, 30 Apr 2008 12:27:09 -0700 An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a spacer is created on the polysilicon shape, the... http://www.freshpatents.com/Flexible-fingerprint-sensor-dt20080424ptan20080093687.php Wed, 30 Apr 2008 12:27:09 -0700 A flexible pressure sensor has a first set of substantially parallel conductors in the x direction, a second set of substantially parallel conductors in the y direction, and a composite material disposed between the first set and second set of conductors. The composite material is capable of returning to substantially... http://www.freshpatents.com/Mems-device-dt20080424ptan20080093685.php Wed, 30 Apr 2008 12:27:09 -0700 A microelectromechanical system (MEMS) device includes a semiconductor substrate, a MEMS including a fixed electrode and a movable electrode formed on the semiconductor substrate through an insulating layer, and a well formed in the semiconductor substrate below the fixed electrode. The well is one of an n-type well and a... http://www.freshpatents.com/Mems-device-and-fabrication-method-thereof-dt20080424ptan20080093684.php Wed, 30 Apr 2008 12:27:09 -0700 A micro electro mechanical system (MEMS) device includes: a fixed electrode made of silicon and provided above a semiconductor substrate; a movable electrode made of silicon and arranged in a mechanically movable manner by having a gap from the semiconductor substrate; and a wiring layered part that is provided around... http://www.freshpatents.com/Electromechanical-non-volatile-memory-devices-dt20080424ptan20080093686.php Wed, 30 Apr 2008 12:27:09 -0700 Electromechanical non-volatile memory devices are provided including a semiconductor substrate having an upper surface including insulation characteristics. A first electrode pattern is provided on the semiconductor substrate. The first electrode pattern exposes portions of a surface of the semiconductor substrate therethrough. A conformal bit line is provided on the first... http://www.freshpatents.com/Flip-chip-assembly-of-protected-micromechanical-devices-dt20080424ptan20080093689.php Wed, 30 Apr 2008 12:27:09 -0700 A low-cost ceramic package, in land-grid array or ball-grid array configuration, for micromechanical components is fabricated by coating the whole integrated circuits wafer with a protective material, selectively etching the coating for solder ball attachment, singulating the chips, flip-chip assembling a chip onto the opening of a ceramic substrate, underfilling... http://www.freshpatents.com/Mem-switching-device-and-method-for-making-same-dt20080424ptan20080093691.php Wed, 30 Apr 2008 12:27:09 -0700 A MEM device and method for fabricating a MEM device. A MEM device comprising a lever mechanism residing along a substrate is disclosed. A contact material is deposited on a first surface of the lever mechanism. In one arrangement, the first surface is disposed towards the substrate. A first contact... http://www.freshpatents.com/Micromechanical-component-having-a-monolithically-integrated-circuit-and-method-for-manufacturing-a-component-dt20080424ptan20080093690.php Wed, 30 Apr 2008 12:27:09 -0700 A micromechanical component and a method for manufacturing such a component, the component having a micromechanical structure and an integrated circuit, the micromechanical structure being monolithically integrated into the circuit, the circuit being provided in a circuit area of the substrate, and the micromechanical structure being provided in a sensor... http://www.freshpatents.com/Process-for-modifying-offset-voltage-characteristics-of-an-interferometric-modulator-dt20080424ptan20080093688.php Wed, 30 Apr 2008 12:27:09 -0700 An interferometric modulator manufactured according to a particular set of processing parameters may have a non-zero offset voltage. A process has been developed for modifying the processing parameters to shift the non-zero offset voltage closer to zero. For example, the process may involve identifying a set of processing parameters for... http://www.freshpatents.com/Audio-processing-device-with-encapsulated-electronic-component-dt20080424ptan20080093692.php Wed, 30 Apr 2008 12:27:09 -0700 The invention regards an audio processing device with at least one encapsulated electronic component mounted and electrically connected to electric leads in a mounting substrate. Further electric components are mounted for connection with the encapsulated electronic component through the substrate and the encapsulation material is moulded onto the substrate. According... http://www.freshpatents.com/Nanowire-sensor-with-variant-selectively-interactive-segments-dt20080424ptan20080093693.php Wed, 30 Apr 2008 12:27:09 -0700 A nanowire sensor is operable to detect one or more species. The nanowire sensor includes a nanowire having a plurality of variant selectively interactive segments. Each of the variant selectively interactive segments are configured to simultaneously interact with the species to modulate the conductance of the nanowire for detecting the... http://www.freshpatents.com/Method-for-manufacturing-a-semcoductor-component-and-a-semiconductor-component-in-particular-a-diaphragm-sensor-dt20080424ptan20080093694.php Wed, 30 Apr 2008 12:27:09 -0700 In a method for manufacturing a semiconductor component having a semiconductor substrate, a flat, porous diaphragm layer and a cavity underneath the porous diaphragm layer are produced to form unsupported structures for a component. In a first approach, the semiconductor substrate may receive a doping in the diaphragm region that... http://www.freshpatents.com/Image-sensor-and-fabricating-method-thereof-dt20080424ptan20080093695.php Wed, 30 Apr 2008 12:27:09 -0700 An image sensor including a substrate having a plurality of semiconductor devices formed thereon, an interconnection layer disposed on the substrate, and a plurality of isolated photo-diodes embedded in the interconnection layer is provided. The isolated photo-diodes are located above the semiconductor devices and electrically connected to the semiconductor devices... http://www.freshpatents.com/Solid-state-imaging-device-and-manufacturing-method-thereof-dt20080424ptan20080093696.php Wed, 30 Apr 2008 12:27:09 -0700 A light shielding film, an insulating layer, a planarizing layer, and a color filter are formed consecutively on a semiconductor substrate having plural photodiodes in a matrix arrangement. A transparent conductive film is formed on the color filter, and micro-lenses are formed directly on the conductive film such that they... http://www.freshpatents.com/Semiconductor-device-and-manufacturing-method-thereof-dt20080424ptan20080093697.php Wed, 30 Apr 2008 12:27:09 -0700 A second impurity region is surrounded by a first impurity region at a first main surface. A third impurity region of the first main surface sandwiches the second impurity region with the first impurity region. Fourth and fifth impurity regions of a second main surface sandwich the first impurity region... http://www.freshpatents.com/Nanostructure-arrays-and-methods-for-forming-same-dt20080424ptan20080093698.php Wed, 30 Apr 2008 12:27:09 -0700 A method for forming an array of elongated nanostructures, includes in one embodiment, providing a substrate, providing a template having a plurality of pores on the substrate, and removing portions of the substrate under the plurality of pores of the template to form a plurality of cavities. A catalyst is... http://www.freshpatents.com/Semiconductor-device-and-method-of-manufacturing-the-same-dt20080424ptan20080093699.php Wed, 30 Apr 2008 12:27:09 -0700 The semiconductor device includes a plurality of transistors at least having different channel widths from each other. Threshold voltages of those transistors are set to be substantially equal to each other, by using both of substantially the same channel dose for each of those transistors, and work function control using... http://www.freshpatents.com/Semiconductor-device-and-method-for-fabricating-the-same-dt20080424ptan20080093701.php Wed, 30 Apr 2008 12:27:09 -0700 A semiconductor device includes a device isolation layer on a semiconductor substrate defining an active region in the semiconductor substrate, a low voltage well of a first conductivity type in the active region of the semiconductor substrate, a high voltage impurity region of a second conductivity type in the active... http://www.freshpatents.com/Semiconductor-device-and-method-for-operating-the-same-dt20080424ptan20080093700.php Wed, 30 Apr 2008 12:27:09 -0700 A method for operating a semiconductor device is described, the semiconductor device including a high-voltage device and a control circuit coupled to each other on a single chip and the high-voltage device including a source, a drain and a gate. This method applies a drain voltage of about 20V or... http://www.freshpatents.com/Semiconductor-device-having-a-passive-device-dt20080424ptan20080093702.php Wed, 30 Apr 2008 12:27:09 -0700 The present invention relates to a semiconductor device having a passive device. The semiconductor device includes a substrate and at least one passive device. The substrate has at least one via. The via has at least two conductive elements therein. The conductive elements are not electrically connected to each other.... http://www.freshpatents.com/Electrical-fuse-and-method-of-making-dt20080424ptan20080093703.php Wed, 30 Apr 2008 12:27:09 -0700 A semiconductor fuse and methods of making the same. The fuse includes a fuse element and a compressive stress liner that reduces the electro-migration resistance of the fuse element. The method includes forming a substrate, forming a trench feature in the substrate, depositing fuse material in the trench feature, depositing... http://www.freshpatents.com/Semiconductor-device-having-moisture-proof-dam-and-method-of-fabricating-the-same-dt20080424ptan20080093704.php Wed, 30 Apr 2008 12:27:09 -0700 A semiconductor device having a moisture-proof dam and a method of fabricating the same are provided. The semiconductor device includes an interlayer insulating layer provided on a substrate having a fuse region. A fuse guard dam is provided on the interlayer insulating layer to surround the fuse region. A cover... http://www.freshpatents.com/Semiconductor-device-preventing-bridge-between-fuse-pattern-and-guard-ring-dt20080424ptan20080093705.php Wed, 30 Apr 2008 12:27:09 -0700 A semiconductor device having a fuse structure that can prevent a bridge between a fuse pattern and a guard ring, and a method of fabricating the same are provided. The fuse pattern formed on a multiple-layered metal interconnect layer is stepped shape increasing a vertical distance between the fuse pattern... http://www.freshpatents.com/Semiconductor-device-and-method-of-manufacturing-the-same-dt20080424ptan20080093706.php Wed, 30 Apr 2008 12:27:09 -0700 Provided is a semiconductor device that solves the problem of a conventional semiconductor device. In the conventional semiconductor device, a resistor is connected with a wiring layer via a contact hole, so that a reduction in parasitic capacitance of the resistor and a substrate is hard to be accomplished. In... http://www.freshpatents.com/Semiconductor-device-provided-with-floating-electrode-dt20080424ptan20080093707.php Wed, 30 Apr 2008 12:27:09 -0700 A semiconductor device has a first conductivity-type first semiconductor region, a second conductivity-type second semiconductor region and a second conductivity-type third semiconductor region both located on or above the first semiconductor region, a second conductivity-type fourth semiconductor region between the second semiconductor region and the third semiconductor region, and a... http://www.freshpatents.com/Semiconductor-device-and-manufacturing-method-thereof-dt20080424ptan20080093708.php Wed, 30 Apr 2008 12:27:09 -0700 A manufacturing method of a semiconductor device formed in a chip size package is improved to enhance a yield and reliability. A window to expose first wirings is formed only in a region of a semiconductor substrate where the first wirings exist. As a result, area of the semiconductor substrate... http://www.freshpatents.com/Manufacturing-method-of-semiconductor-device-and-semiconductor-device-dt20080424ptan20080093709.php Wed, 30 Apr 2008 12:27:09 -0700 A semiconductor substrate in a state that an inter-layer insulation film is formed is loaded in a chamber, air in the chamber is purged by introducing a large amount of a nitrogen gas in the chamber, and an atmospheric gas in the chamber is substituted with a nitrogen gas. After... http://www.freshpatents.com/Hard-mask-arrangement-contact-arrangement-and-methods-of-patterning-a-substrate-and-manufacturing-a-contact-arrangement-dt20080424ptan20080093710.php Wed, 30 Apr 2008 12:27:09 -0700 An interlayer is disposed on a pattern surface of a substrate. A buried hard mask may be provided on the interlayer. The buried hard mask includes a template opening having a template length along a line axis and a template width perpendicular thereto. The buried hard mask is filled with... http://www.freshpatents.com/Dielectric-layers-and-methods-of-forming-the-same-dt20080424ptan20080093711.php Wed, 30 Apr 2008 12:27:09 -0700 High dielectric constant (high-k) materials are formed directly over oxidation-susceptible conductors such as silicon. A discontinuous layer is formed, with gaps between grains of the high-k material. Exposed conductor underneath the grain boundaries is oxidized or nitridized to form, e.g., silicon dioxide or silicon nitride, when exposed to oxygen or... http://www.freshpatents.com/Chip-with-light-protection-layer-dt20080424ptan20080093712.php Wed, 30 Apr 2008 12:27:09 -0700 In the case of a chip (1) having an integrated circuit (2), a dielectric mirror coating (3) having at least two dielectric layers (6, 7, . . . H, I, H) is applied as light protection means for the at least one integrated circuit (2) on at least one portion... http://www.freshpatents.com/Metal-clad-fiber-optics-for-enhanced-heat-dissipation-dt20080424ptan20080093713.php Wed, 30 Apr 2008 12:27:09 -0700 An integrated optical I/O and semiconductor chip with a direct liquid jet impingement cooling assembly are disclosed. Contrary to other solutions for packaging an optical I/O with a semiconductor die, this assembly makes use of a metal clad fiber, e.g. copper, which will actually enhance cooling performance rather than create... http://www.freshpatents.com/Semiconductor-device-and-method-of-fabricating-the-same-dt20080424ptan20080093714.php Wed, 30 Apr 2008 12:27:09 -0700 A semiconductor device and method of fabricating the same reduce the likelihood of the occurrence of electrical defects. The device includes a first interlayer insulating film on a semiconductor substrate; a contact pad spacer on the first interlayer insulating film; and a contact pad in the first interlayer insulating film... http://www.freshpatents.com/Leadframe-and-mold-compound-interlock-in-packaged-semiconductor-device-dt20080424ptan20080093715.php Wed, 30 Apr 2008 12:27:09 -0700 An interference interlock between leadframe features and a mold compound is provided in a packaged semiconductor device by exposing at least one predetermined surface area to an etching process prior to a molding step. This produces an etched recess with a recessed wall delimited by a step wall, generally perpendicular... http://www.freshpatents.com/Semiconductor-device-and-method-of-manufacturing-semiconductor-device-dt20080424ptan20080093716.php Wed, 30 Apr 2008 12:27:09 -0700 A semiconductor device of the present invention includes a lead frame having an island portion having a roughened upper surface and side faces, and an unroughened lower surface, and also having a plurality of leads having roughened inner lead portions and unroughened outer lead portions; a semiconductor chip placed on... http://www.freshpatents.com/Leadframe-of-a-leadless-flip-chip-package-and-method-for-manufacturing-the-same-dt20080424ptan20080093717.php Wed, 30 Apr 2008 12:27:09 -0700 A leadframe of a leadless flip-chip package includes a plurality of inner leads, a nonconductive ink layer and a solder mask layer. The inner leads have a plurality of bump-connecting terminals, a plurality of outer terminals and a plurality of redistribution lead portions. A half-etched recession is formed on lower... http://www.freshpatents.com/Semiconductor-component-and-method-of-manufacture-dt20080424ptan20080093718.php Wed, 30 Apr 2008 12:27:09 -0700 A semiconductor component having a semiconductor chip mounted on a packaging substrate and a method for manufacturing the semiconductor component that uses batch processing steps for fabricating the packaging substrate. A heatsink is formed using an injection molding process. The heatsink has a front surface for mating with a semiconductor... http://www.freshpatents.com/Chip-package-structure-dt20080424ptan20080093719.php Wed, 30 Apr 2008 12:27:09 -0700 A chip package structure including a chip, a leadframe, multiple bonding wires and an encapsulant is provided. The chip has an active surface and multiple contacts. The contacts are located on one side of the active surface. The chip is fixed under the leadframe. The leadframe has multiple first inner... http://www.freshpatents.com/Single-chip-usb-packages-with-contact-pins-cover-dt20080424ptan20080093720.php Wed, 30 Apr 2008 12:27:09 -0700 A low-profile Universal-Serial-Bus (USB) assembly includes a modular USB core component that is retractably mounted into an external housing. The modular USB core component includes a PCBA in which all passive components and unpackaged IC chips are attached to a single side of a PCB opposite to the metal contacts.... http://www.freshpatents.com/Chip-package-for-image-sensor-and-method-of-manufacturing-the-same-dt20080424ptan20080093721.php Wed, 30 Apr 2008 12:27:09 -0700 A chip package for an image sensor includes a first semiconductor chip having a first surface where a photographing device and a first circuit pattern are formed and a second surface that is opposite to the first surface where a second circuit pattern is formed. The first and second circuit... http://www.freshpatents.com/Encapsulation-type-semiconductor-device-and-manufacturing-method-thereof-dt20080424ptan20080093722.php Wed, 30 Apr 2008 12:27:09 -0700 An encapsulation type semiconductor device and a manufacturing method of the encapsulation type semiconductor device are disclosed. The encapsulation type semiconductor device includes a substrate provided with a concave portion which concaves in a direction from a first principal surface portion to a second principal surface portion. A first semiconductor... http://www.freshpatents.com/Passive-placement-in-wire-bonded-microelectronics-dt20080424ptan20080093723.php Wed, 30 Apr 2008 12:27:09 -0700 A microelectronic assembly includes a first microelectronic device electrically coupled with a second microelectronic device via wire bond attachment, the first microelectronic device being structurally coupled with the second microelectronic device via a polymer adhesive, and one or more passive(s) coupled with the first microelectronic device wherein at least one... http://www.freshpatents.com/Semiconductor-package-preventing-warping-and-wire-severing-defects-and-method-of-manufacturing-the-semiconductor-package-dt20080424ptan20080093725.php Wed, 30 Apr 2008 12:27:09 -0700 Provided are a semiconductor package and a method of manufacturing the same. The semiconductor package includes a circuit substrate having a slit inside the circuit substrate, a semiconductor chip formed on an upper surface of the circuit substrate, a wire connecting the semiconductor chip and the circuit substrate through the... http://www.freshpatents.com/Stackable-micropackages-and-stacked-modules-dt20080424ptan20080093724.php Wed, 30 Apr 2008 12:27:09 -0700 The present invention provides a system and method for devising stackable assemblies that may be then stacked to create a stacked circuit module. One or more integrated circuit (IC) die are disposed on one or more sides of a redistribution substrate that is preferably flexible circuitry. In some preferred embodiments,... http://www.freshpatents.com/Continuously-referencing-signals-over-multiple-layers-in-laminate-packages-dt20080424ptan20080093726.php Wed, 30 Apr 2008 12:27:09 -0700 A mechanism for continuously referencing signals over multiple layers in laminate packages provides a continuous path for signals from one layer to another while using the ideal voltage reference for all areas of the package and still avoiding discontinuities in the voltage reference. A reference plane adjustment engine analyzes a... http://www.freshpatents.com/Metallised-film-for-sheet-contacting-dt20080424ptan20080093727.php Wed, 30 Apr 2008 12:27:09 -0700 An embodiment of the present invention discloses a method for contacting at least one electrical contact surface on a surface of a substrate and/or at least one component arranged on the substrate, especially a semiconductor chip. The method includes the following steps: at least one insulating film consisting of an... http://www.freshpatents.com/Integrated-circuit-component-with-passivation-layer-and-methods-for-making-the-same-dt20080424ptan20080093728.php Wed, 30 Apr 2008 12:27:09 -0700 The invention relates to a semiconductor component (1) comprising a semiconductor chip (3) provided with a passivation layer (2), and to methods for producing the same. In this case, the passivation layer (2) covers the topmost interconnect structure (4) of the semiconductor chip (1) whilst leaving contact areas (5) free.... http://www.freshpatents.com/Semiconductor-arrangement-semiconductor-module-and-method-for-connecting-a-semiconductor-chip-to-a-ceramic-substrate-dt20080424ptan20080093729.php Wed, 30 Apr 2008 12:27:09 -0700 A semiconductor arrangement has a silicon body with a first surface and a second surface and a thick metal layer arranged on at least one surface of the silicon body. The thickness of the thick metal-layer is at least 10 micrometers (μm).... http://www.freshpatents.com/Semiconductor-module-and-semiconductor-device-dt20080424ptan20080093730.php Wed, 30 Apr 2008 12:27:09 -0700 Electrode plates (52, 54) acting as a heat sink are arranged to sandwich a power transistor (Q1) and a diode (D1). Electrode plates (52, 54) at their surfaces opposite cooling elements (62, 64) at a portion opposite power transistor (Q1) and diode (D1) are formed to be smaller in thickness... http://www.freshpatents.com/Cooled-integrated-circuit-dt20080424ptan20080093731.php Wed, 30 Apr 2008 12:27:09 -0700 The invention relates to an integrated circuit (1) having a plurality of substrate layers (2), active and/or passive components (3) embedded in the substrate layers (2), high-frequency lines conducted to the components (3) through the substrate layers (2), and cooling channels (6) for the dissipation of heat. The inventive circuit... http://www.freshpatents.com/Packaging-for-high-power-integrated-circuits-using-supercritical-fluid-dt20080424ptan20080093732.php Wed, 30 Apr 2008 12:27:09 -0700 A package for a semiconductor chip or other heat producing device has a supporting substrate to which the devices mount and electrically connect. An enclosure is formed over the heat producing devices and filled with a supercritical fluid that transports heat from the devices to a heat sink in thermal... http://www.freshpatents.com/Chip-package-and-manufacturing-method-thereof-dt20080424ptan20080093733.php Wed, 30 Apr 2008 12:27:09 -0700 A chip package including a carrier, at least one chip, a heat spreader, and a thermal interface material (TIM) is provided. The chip is disposed on the carrier and is electrically connected to the carrier. The heat spreader is disposed on the carrier, wherein the heat spreader and the carrier... http://www.freshpatents.com/High-density-ic-module-dt20080424ptan20080093734.php Wed, 30 Apr 2008 12:27:09 -0700 A system a method for assembling dual-die integrated circuit packages using thermocompression bonding or thermosonic bonding to bond a second die to a substrate opposite a first die bonded to the substrate. The second die is bonded using heat conducted through the first die to the substrate, and optionally through... http://www.freshpatents.com/Potted-integrated-circuit-device-with-aluminum-case-dt20080424ptan20080093735.php Wed, 30 Apr 2008 12:27:09 -0700 An integrated circuit device includes a die, a lead, and an electrically-conductive structure that is arranged to facilitate electrical communication between the die and the lead. The device also includes a potting material, in which the electrically conductive structure, the die, and at least part of the lead are embedded.... http://www.freshpatents.com/Semiconductor-device-dt20080424ptan20080093736.php Wed, 30 Apr 2008 12:27:09 -0700 A semiconductor die has a top surface and a bottom surface. A source contact, a gate contact and a gate finger are formed on the top surface. The source contact has a slit and the gate finger is disposed in the slit of the source contact. A drain contact is... http://www.freshpatents.com/Capacitive-semiconductor-sensor-dt20080424ptan20080093740.php Wed, 30 Apr 2008 12:27:09 -0700 A capacitive semiconductor sensor includes a sensor chip, a circuit chip, a plurality of bumps, and a plurality of dummy bumps. The sensor chip includes a dynamic quantity detector, which has a detection axis in one direction. The circuit chip includes a signal processing circuit. The sensor chip and the... http://www.freshpatents.com/Chip-structure-and-wafer-structure-dt20080424ptan20080093738.php Wed, 30 Apr 2008 12:27:09 -0700 A chip structure including a substrate, at least one pad, at least one protruding pattern, a passivation layer, and at least one bump is provided. The substrate has a circuit unit. The pad and the protruding pattern are disposed on the circuit unit, and the pad is surrounded by the... http://www.freshpatents.com/Integrated-circuit-with-a-reduced-pad-bump-area-and-the-manufacturing-method-thereof-dt20080424ptan20080093737.php Wed, 30 Apr 2008 12:27:09 -0700 An integrated circuit with a reduced pad bump area and the manufacturing method thereof are disclosed. The integrated circuit includes a semiconductor substrate, an interconnection layer, a passivation layer, and at least a bump. The semiconductor substrate has a semiconductor device thereon. The interconnection layer is disposed on the semiconductor... http://www.freshpatents.com/Semiconductor-mounting-substrate-and-method-for-manufacturing-the-same-dt20080424ptan20080093739.php Wed, 30 Apr 2008 12:27:09 -0700 A semiconductor mounting substrate according to the present invention comprises: a substrate; a semiconductor device, mounted on this substrate; solder bumps, which connect the semiconductor device and the substrate; a first resin, filled in a space between the semiconductor device and the substrate; and electronic components, mounted on a face... http://www.freshpatents.com/Semiconductor-device-and-method-of-fabricating-the-same-dt20080424ptan20080093741.php Wed, 30 Apr 2008 12:27:09 -0700 In a semiconductor device and a method of fabricating the same, the semiconductor device includes a contact pad in a first interlayer insulating layer on a semiconductor substrate, a contact hole in a second interlayer insulating layer on the first interlayer insulating layer, selectively exposing the contact pad, a contact... http://www.freshpatents.com/Anodization-dt20080424ptan20080093744.php Wed, 30 Apr 2008 12:27:09 -0700 Embodiments of anodization are disclosed.... http://www.freshpatents.com/Sub-lithographic-nano-interconnect-structures-and-method-for-forming-same-dt20080424ptan20080093743.php Wed, 30 Apr 2008 12:27:09 -0700 A method to form interconnect structures including nano-scale, e.g., sub-lithographic, lines and vias for future generation of semiconductor technology using self-assembly block copolymers that can be placed at a specific location using a pre-fabricated hard mask pattern is provided. The inventive method provides an interconnect structure in which the line... http://www.freshpatents.com/System-for-shielding-integrated-circuits-dt20080424ptan20080093742.php Wed, 30 Apr 2008 12:27:09 -0700 A method for adding an additional layer to an integrated circuit, the method including providing an integrated circuit having an interconnect layer, depositing, over substantially all of an exposed surface of the integrated circuit, an additional layer of material whose conductivity can be altered, and selectively altering the conductivity of... http://www.freshpatents.com/High-performance-system-on-chip-using-post-passivation-process-dt20080424ptan20080093745.php Wed, 30 Apr 2008 12:27:09 -0700 The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting... http://www.freshpatents.com/Semiconductor-wafer-having-embedded-electroplating-current-paths-to-provide-uniform-plating-over-wafer-surface-dt20080424ptan20080093746.php Wed, 30 Apr 2008 12:27:09 -0700 A semiconductor wafer having multi-layer metallization structures that are fabricated to include embedded interconnection structures which serve as low-resistance electroplating current paths to conduct bulk electroplating current fed to portions of a metallic seed layer at peripheral surface regions of the wafer to portions of the metallic seed layer at... http://www.freshpatents.com/Three-dimensional-device-integration-method-and-integrated-device-dt20080424ptan20080093747.php Wed, 30 Apr 2008 12:27:09 -0700 A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a... http://www.freshpatents.com/Semiconductor-package-and-fabrication-process-thereof-dt20080424ptan20080093748.php Wed, 30 Apr 2008 12:27:09 -0700 A semiconductor package mainly includes a chip, a substrate, an encapsulant, a plurality of external terminals and a stress release layer. The substrate has an upper surface and a lower surface. The chip is disposed on the upper surface of the substrate by a chip-attached layer and electrically connected to... http://www.freshpatents.com/Partial-solder-mask-defined-pad-design-dt20080424ptan20080093749.php Wed, 30 Apr 2008 12:27:09 -0700 A solder ball pad that includes a substrate and a bonding pad attached to the substrate. The bonding pad has a bonding pad surface and a bonding pad edge. The solder ball pad also includes a solder mask attached to the substrate in which the solder mask at least partially...