http://www.freshpatents.com/Data-processing--design-and-analysis-of-circuit-or-semiconductor-mask-dtnewntc716.php USPTO Class 716 - Data processing: design and analysis of circuit or semiconductor mask en-us Mon, 17 Jun 2013 13:45:13 -0700 1000 Wednesday Thursday Friday Saturday Sunday 141 31 http://www.freshpatents.com/index.php?rss=true http://www.freshpatents.com/images/freshpatentsnav_rss.gif http://www.freshpatents.com/-dt20130613ptan20130152025.php Mon, 17 Jun 2013 13:45:13 -0700 A method and system for computing Fourier coefficients for a Fourier representation of a mask transmission function for a lithography mask. The method includes: sampling a polygon of a mask pattern of the lithography mask to obtain an indicator function which defines the polygon, performing a Fourier Transform on the... http://www.freshpatents.com/-dt20130613ptan20130152027.php Mon, 17 Jun 2013 13:45:13 -0700 A method of for compensating for variations in structures of an integrated circuit. The method includes (a) selecting a mask design shape and selecting a region of the mask design shape; (b) applying a model-based optical proximity correction to all of the mask design shape; and after (b), (c) applying... http://www.freshpatents.com/-dt20130613ptan20130152026.php Mon, 17 Jun 2013 13:45:13 -0700 A technique for providing information about defects in a mask pattern is described. In this technique, defects in the mask pattern may be determined based on differences between a calculated pattern produced at an image plane in the photolithographic process, when the mask pattern, illuminated by an associated source pattern,... http://www.freshpatents.com/-dt20130613ptan20130152028.php Mon, 17 Jun 2013 13:45:13 -0700 A computer-implemented method of determining threshold voltage levels within a macro of integrated circuit cells. In one embodiment, the method includes: referencing a library of the integrated circuit cells in the macro; estimating a leakage power and a dynamic power for a first integrated circuit cell in the macro; comparing... http://www.freshpatents.com/-dt20130613ptan20130152029.php Mon, 17 Jun 2013 13:45:13 -0700 Methods for allocating spare latch circuits to logic blocks in an integrated circuit design are provided. A method includes determining logic blocks in the design and determining and determining an allocation of spare latch circuits among the logic blocks based on respective attributes of the logic blocks. The method further... http://www.freshpatents.com/-dt20130613ptan20130152031.php Mon, 17 Jun 2013 13:45:13 -0700 A method of managing the configuration, design parameters, and functionality of an integrated circuit (IC) design using a hardware description language (HDL). Instructions can be added, subtracted, or generated by the designer interactively during the design process, and customized HDL descriptions of the IC design are generated through the use... http://www.freshpatents.com/-dt20130613ptan20130152030.php Mon, 17 Jun 2013 13:45:13 -0700 A method and apparatus are provided for use in synthesis of RTL integrated circuit design to determine the functional equivalence of designs. For example, the receiver receives a plurality of designs for synthesis in RTL and a data flow graph is derived for each design. Internal bit widths in the... http://www.freshpatents.com/-dt20130613ptan20130152032.php Mon, 17 Jun 2013 13:45:13 -0700 A method is provided for inspecting a chip layout. The method includes providing a chip layout having a plurality of patterns designed according to a design rule and performing a first inspection to the plurality of patterns according to the design rule. The method also includes determining patterns violating the... http://www.freshpatents.com/-dt20130613ptan20130152033.php Mon, 17 Jun 2013 13:45:13 -0700 The present invention provides a Technology Computer Aided Design (TCAD) emulation calibration method of a Silicon On Insulator (SOI) field effect transistor, where process emulation Metal Oxide Semiconductor (MOS) device structures with different channel lengths Lgate are obtained by establishing a TCAD process emulation program; based on the process emulation... http://www.freshpatents.com/-dt20130613ptan20130152034.php Mon, 17 Jun 2013 13:45:13 -0700 A system for, and method of, reducing IC timing derating for a path in an integrated circuit design. In one embodiment, the system includes an electronic design automation tool configured to (1) extract circuit data regarding cells in the path and (2) calculate a timing derating for the path based... http://www.freshpatents.com/-dt20130613ptan20130152035.php Mon, 17 Jun 2013 13:45:13 -0700 Embodiments of the claimed subject matter are directed to methods and a system that use a standardized grid of clock buffers to automatically route clocks according to a uniform clock grid throughout an ASIC of a non-uniform arrangement of non-uniformly sized logic partitions. According to one embodiment, clock sources and... http://www.freshpatents.com/-dt20130613ptan20130152036.php Mon, 17 Jun 2013 13:45:13 -0700 Disclosed is a technique for providing minimal sequential overhead in a flip-flop circuit. Equalization of setup times is achieved in one embodiment. In addition, delays in clock to Q can be equalized for both rising data transitions and falling data transitions. Large setup times are not required since optimization techniques... http://www.freshpatents.com/-dt20130613ptan20130152037.php Mon, 17 Jun 2013 13:45:13 -0700 A computer aided design system comprises an interface creating module, a reference layer setting module, a detecting module and a signing module. The interface module creates a parameter setting interface to select at least one net being composed of a plurality of cline segments, and set a stack distance. The...