http://www.freshpatents.com/Data-processing--design-and-analysis-of-circuit-or-semiconductor-mask-dtnewntc716.php USPTO Class 716 - Data processing: design and analysis of circuit or semiconductor mask en-us Wed, 30 Apr 2008 12:40:24 -0700 1000 Wednesday Thursday Friday Saturday Sunday 141 31 http://www.freshpatents.com/index.php?rss=true http://www.freshpatents.com/images/freshpatentsnav_rss.gif http://www.freshpatents.com/Automatic-voltage-drop-optimization-dt20080424ptan20080098335.php Wed, 30 Apr 2008 12:40:24 -0700 To minimize the voltage drops in an electronic circuit, existing instances are moved and decoupling capacitors are automatically inserted according to an algorithm. A model of the voltage drop on a row of gate elements is presented. The model allows for rapid computations of the effect of a particular move... http://www.freshpatents.com/Design-layout-generating-method-for-semiconductor-integrated-circuits-dt20080424ptan20080098341.php Wed, 30 Apr 2008 12:40:24 -0700 A design layout generating method for generating a design pattern of a semiconductor integrated circuit is disclosed. This method comprises modifying a first modification area extracted from a design layout by a first modifying method, and modifying a second modification area extracted from the design layout so as to include... http://www.freshpatents.com/Method-and-process-for-design-of-integrated-circuits-using-regular-geometry-patterns-to-obtain-geometrically-consistent-component-features-dt20080424ptan20080098334.php Wed, 30 Apr 2008 12:40:24 -0700 The invention provides a method and process for designing an integrated circuit based on using the results from both 1) a specific set of silicon test structure characterizations and 2) the decomposition of logic into combinations of simple logic primitives, from which a set of logic bricks are derived that... http://www.freshpatents.com/Compiler-and-logic-circuit-design-method-dt20080424ptan20080098336.php Wed, 30 Apr 2008 12:40:24 -0700 A compiler in which pseudo C descriptions (1) that are capable of describing parallel operations at a statement level and at a cycle precision by clock boundaries and register assignment statements are input, the register assignment statements are identified (S2), so as to generate executable C descriptions (3), to extract... http://www.freshpatents.com/Method-of-forming-guard-ring-parameterized-cell-structure-in-a-hierarchical-parameterized-cell-design-checking-and-verification-system-dt20080424ptan20080098337.php Wed, 30 Apr 2008 12:40:24 -0700 The invention displays a guard ring within an integrated circuit design by determining positions of the logic devices within the integrated circuit design, incorporating the guard ring into the integrated circuit design, and displaying the logic devices and the guard ring either graphically, semantically, or symbolically in a single display.... http://www.freshpatents.com/Method-system-and-computer-program-product-for-generating-and-verifying-isolation-logic-modules-in-design-of-integrated-circuits-dt20080424ptan20080098338.php Wed, 30 Apr 2008 12:40:24 -0700 A method, system and computer program product for generating and verifying the correctness of isolation logic modules in design of integrated circuits (ICs). The method disclosed generates an isolation logic module for each power domain specified by a user, instantiates the generated module in a pre-determined wakeup domain, and then... http://www.freshpatents.com/Racecheck--a-race-logic-analyzer-program-for-digital-integrated-circuits-dt20080424ptan20080098339.php Wed, 30 Apr 2008 12:40:24 -0700 Techniques a race logic analysis on an integrated circuit (IC) design are described herein. In one embodiment, all hardware description language (HDL) defined system functions and/or tasks that have one or more side-effects when invoked in a first HDL language, but not when the same HDL-defined system functions/tasks are invoked... http://www.freshpatents.com/Method-for-designing-block-placement-and-power-distribution-of-semiconductor-integrated-circuit-dt20080424ptan20080098340.php Wed, 30 Apr 2008 12:40:24 -0700 The present invention relates to a method for designing initial placement of functional blocks and designing power distribution network of a semiconductor integrated circuit in the next stage of architecture level design of integrated circuit, which estimates the area and the quantity of power consumption of functional blocks and integrated... http://www.freshpatents.com/Semiconductor-integrated-circuit-designing-method-semiconductor-integrated-circuit-device-and-electronic-device-dt20080424ptan20080098342.php Wed, 30 Apr 2008 12:40:24 -0700 A simple method for designing a semiconductor integrated circuit having the ZSCCMOS structure is provided. For each kind of primitive logic gate, a logic gate cell H and a layout cell H each having a high-potential power supply end connected to VDD and a low potential power supply end connected... http://www.freshpatents.com/System-and-method-for-text-based-placement-engine-for-custom-circuit-design-dt20080424ptan20080098343.php Wed, 30 Apr 2008 12:40:24 -0700 A system and method that uses a text-based script file to capture a circuit design and allows a circuit designer to manipulate the script file. The circuit designer can add, delete, or move components using various tags and commands that are stored in the script file. When the design is...