http://www.freshpatents.com/Electrical-computers--arithmetic-processing-and-calculating-dtnewntc708.php USPTO Class 708 - Electrical computers: arithmetic processing and calculating en-us Tue, 18 Aug 2009 23:34:47 -0700 1000 Wednesday Thursday Friday Saturday Sunday 141 31 http://www.freshpatents.com/index.php?rss=true http://www.freshpatents.com/images/freshpatentsnav_rss.gif http://www.freshpatents.com/System-and-method-for-determining-a-grouping-of-segments-within-a-market-dt20090813ptan20090204655.php Tue, 18 Aug 2009 23:34:47 -0700 A method for determining a grouping of segments within a market. The method includes forming a bias mitigated square matrix from a square matrix populated with second choice data, and forming a compressed matrix from the bias mitigated square matrix. Each different segment is initially associated with a row of... http://www.freshpatents.com/Pseudo-random-number-generator-and-method-for-generating-a-pseudo-random-number-bit-sequence-dt20090813ptan20090204656.php Tue, 18 Aug 2009 23:34:47 -0700 A pseudo random number generator including a plurality of non-singular feedback shift registers each configured to output a bit-sequence. At least a first of the plurality of non-singular feedback shift registers has one or more first cycles of a length less than or equal to two, and a second of... http://www.freshpatents.com/Hybrid-random-number-generator-dt20090813ptan20090204657.php Tue, 18 Aug 2009 23:34:47 -0700 A hybrid random number generator (HRNG) including an output, a combinational logic, a TRNG, and a PRNG. The HRNG is configurable to operate in a first and a second mode, wherein in the first mode the PRNG is serially connected between the TRNG and the output and the TRNG intermittently... http://www.freshpatents.com/Decimal-computing-apparatus-electronic-device-connectable-decimal-computing-apparatus-arithmetic-operation-apparatus-arithmetic-operation-control-apparatus-and-program-recorded-recording-medium-dt20090813ptan20090204658.php Tue, 18 Aug 2009 23:34:47 -0700 A decimal calculation apparatus, which performs multidigit decimal calculation with the number of calculation digits set in a calculation instruction, includes a multidigit memory section which stores values with greater numbers of digits than the number of digits of a predetermined digit unit in a plurality of memory areas, a... http://www.freshpatents.com/N-bit-adder-and-corresponding-addition-method-dt20090813ptan20090204659.php Tue, 18 Aug 2009 23:34:47 -0700 An adder is provided for adding input signals including first and second binary input numbers, with N bits each. The adder includes a determination circuit capable of determining the bits of the sum of the input signals. The determination circuit includes an estimating circuit including estimating blocks connected in series,...