http://www.freshpatents.com/Electrical-computers--arithmetic-processing-and-calculating-dtnewntc708.php USPTO Class 708 - Electrical computers: arithmetic processing and calculating en-us Mon, 20 May 2013 13:46:47 -0700 1000 Wednesday Thursday Friday Saturday Sunday 141 31 http://www.freshpatents.com/index.php?rss=true http://www.freshpatents.com/images/freshpatentsnav_rss.gif http://www.freshpatents.com/-dt20130516ptan20130124587.php Mon, 20 May 2013 13:46:47 -0700 A circuit and method of operation for a circuit of a radio system in which a system time is divided into symbols, in which a system clock generator is activated in an operating mode, so that the system time is determined from an output clock signal of the system clock... http://www.freshpatents.com/-dt20130516ptan20130124586.php Mon, 20 May 2013 13:46:47 -0700 An aspect includes an apparatus for evaluating a mathematical function at an input value. The apparatus includes a selector for selecting a mathematical function, an input for a value at which to evaluate the function, an identifier for identifying an interval containing the input value. The interval is described by... http://www.freshpatents.com/-dt20130516ptan20130124589.php Mon, 20 May 2013 13:46:47 -0700 The invention relates to a computer-implemented method for compressing numerical data comprising a structured set of floating point actual values. A floating point value is defined by a sign, an exponent and a mantissa. The method comprises computing a floating point predicted value related to a target actual value of... http://www.freshpatents.com/-dt20130516ptan20130124588.php Mon, 20 May 2013 13:46:47 -0700 According to one aspect of the present disclosure, a method and technique for encoding densely packed decimals is disclosed. The method includes: executing a floating point instruction configured to perform a floating point operation on decimal data in a binary coded decimal (BCD) format; determining whether a result of the... http://www.freshpatents.com/-dt20130516ptan20130124590.php Mon, 20 May 2013 13:46:47 -0700 In one embodiment, a reconfigurable cyclic shifter arrangement has first and second reconfigurable cyclic shifters connected in series that are each selectively and independently configurable to operate in any one of three different modes at a time. In a first mode, the reconfigurable cyclic shifter is configured as four 4×4... http://www.freshpatents.com/-dt20130516ptan20130124591.php Mon, 20 May 2013 13:46:47 -0700 Random numbers are generated using entropic properties associated with circuit hardware. Consistent with one method, a switching voltage regulator circuit is used to generate a random number. Data that is responsive to switching states of the switching voltage regulator circuit is generated. A multi-bit random number is then generated from... http://www.freshpatents.com/-dt20130516ptan20130124592.php Mon, 20 May 2013 13:46:47 -0700 Asynchronous arithmetic units including an asynchronous IEEE 754 compliant floating-point adder and an asynchronous floating point multiplier component. Arithmetic units optimized for lower power consumption and methods for optimization are disclosed.... http://www.freshpatents.com/-dt20130516ptan20130124593.php Mon, 20 May 2013 13:46:47 -0700 The quantifying method for intrinsic data transfer rate of algorithms is provided. The provided quantifying method for an intrinsic data transfer rate includes steps of: detecting whether or not a datum is used; providing a dataflow graph G including n vertices and m edges, and a Laplacian matrix L having... http://www.freshpatents.com/-dt20130516ptan20130124594.php Mon, 20 May 2013 13:46:47 -0700 An integrated circuit comprises divider circuitry configured to perform a division operation. The divider circuitry may be part of an arithmetic logic unit or other computational unit of a microprocessor, digital signal processor, or other type of processor. The divider circuitry iteratively determines bits of a quotient over multiple stages...