http://www.freshpatents.com/Electrical-computers-and-digital-data-processing-systems--input-output-dtnewntc710.php USPTO Class 710 - Electrical computers and digital data processing systems: input/output en-us Wed, 9 Jul 2008 07:49:35 -0700 1000 Wednesday Thursday Friday Saturday Sunday 141 31 http://www.freshpatents.com/index.php?rss=true http://www.freshpatents.com/images/freshpatentsnav_rss.gif http://www.freshpatents.com/Computer-system-and-a-chipset-dt20080703ptan20080162734.php Wed, 9 Jul 2008 07:49:35 -0700 When the entire system is split into plural partitions on chipsets connecting plural processors, IO hubs, and memory controllers, and an OS is operating on each of the partitions, the present invention prevents a failure in a partition from propagating to other partitions. Based on address information or issuer information... http://www.freshpatents.com/Enumeration-of-devices-on-a-memory-channel-dt20080703ptan20080162733.php Wed, 9 Jul 2008 07:49:35 -0700 According to one embodiment, a method is disclosed. The method includes receiving a bit pattern value at a first memory device from a host device via an interface to establish a first sideband address and the first memory device receiving a unique device identification (ID) from the host device.... http://www.freshpatents.com/Methods-and-systems-for-prioritizing-input-outputs-to-storage-devices-dt20080703ptan20080162735.php Wed, 9 Jul 2008 07:49:35 -0700 Embodiments include methods, apparatus, and systems for prioritizing input/outputs (I/Os) to storage devices. One embodiment includes a method that receives an input/output (I/O) command having a group number field and a priority number field at a target device. The method then generates a new priority value based on the group... http://www.freshpatents.com/Image-processing-system-image-forming-system-information-processing-system-image-processing-method-information-processing-method-and-computer-readable-medium-dt20080703ptan20080162736.php Wed, 9 Jul 2008 07:49:35 -0700 An image processing system includes: a receiving section that receives print information including at least a first control command indicating a first print setting and a second control command embedded in a document to be printed and indicating a second print setting; an interpreting section that interprets the first control... http://www.freshpatents.com/Usb-controller-with-full-transfer-automation-dt20080703ptan20080162737.php Wed, 9 Jul 2008 07:49:35 -0700 A USB controller and method of implementing a full transfer automation mode is described. The USB controller may have a host interface module configured to generate hardware logic signals for communication to a backend module having buffer memory. The backend module may be configured to generate hardware logic signals for... http://www.freshpatents.com/Input-output-device-with-configuration-fault-isolation-and-redundant-fault-assist-functionality-dt20080703ptan20080162738.php Wed, 9 Jul 2008 07:49:35 -0700 An I/O device is provided for use in a process control system having a controller operating under a particular version of communication software. The I/O device has a storage device for storing a plurality of potential versions of I/O communication software. An I/O device processor determines the particular version of... http://www.freshpatents.com/Gpio-mux-dynamic-port-configuration-dt20080703ptan20080162739.php Wed, 9 Jul 2008 07:49:35 -0700 Dynamically configurable routing logic coupled between physical I/O ports and special purpose I/O associated with functions within a panel ASIC is disclosed that provide different routing configurations between the physical I/O ports and the special purpose I/O. In one routing configuration, any special purpose output can be coupled to one... http://www.freshpatents.com/Standalone-data-storage-device-electromagnetic-interference-test-setup-and-procedure-dt20080703ptan20080162740.php Wed, 9 Jul 2008 07:49:35 -0700 A method for operating a data storage device having a plurality of sectors and at least one port, each port having a transmitter and a receiver, is disclosed. In one embodiment the method includes coupling at least one of the transmitters to at least one of the receivers, providing power... http://www.freshpatents.com/Wireless-usb-hub-dt20080703ptan20080162741.php Wed, 9 Jul 2008 07:49:35 -0700 This invention provides a Wireless USB hub that includes a first port configured to communicate with a wired USB enabled device, a second port configured to communicate with a first wireless USB enabled device, and a controller that detects the wired USB enabled device and presents the wired USB enabled... http://www.freshpatents.com/Method-of-creating-and-managing-session-between-wireless-universal-serial-bus-host-and-wireless-universal-serial-bus-device-and-providing-wireless-universal-serial-bus-host-and-wireless-universal-serial-bus-device-dt20080703ptan20080162742.php Wed, 9 Jul 2008 07:49:35 -0700 Provided is a session management method of managing a session created between a wireless universal serial bus (USB) host and a wireless USB device through a wireless network, the session management method including: receiving session status messages periodically transmitted for checking a status of the created session; counting a number... http://www.freshpatents.com/Method-and-apparatus-to-select-and-modify-elements-of-vectors-dt20080703ptan20080162743.php Wed, 9 Jul 2008 07:49:35 -0700 A method and apparatus to permute a given set of elements utilizing a permutation network which uses nodes and edges. The permutation network is a minimal network where each of the nodes except the input nodes has N+1 inputs and each of the nodes except the output nodes has N+1... http://www.freshpatents.com/Method-system-and-computer-program-for-monitoring-activities-on-computers-connected-through-a-hardware-switch-dt20080703ptan20080162744.php Wed, 9 Jul 2008 07:49:35 -0700 A technique for monitoring computers connected to a hardware switch. The switch is used to selectively connect a single set of peripheral units to the central unit of a selected one of the computers. In the proposed solution, status information of each non-selected computer is transmitted from the corresponding central... http://www.freshpatents.com/Methods-and-apparatus-for-sharing-a-peripheral-in-a-multi-core-system-dt20080703ptan20080162745.php Wed, 9 Jul 2008 07:49:35 -0700 A queued interface device configured to communicate with a peripheral includes a first interface configured to receive and store a first set of peripheral requests from a first core, a second interface configured to receive and store a second set of peripheral requests from a second core, and an arbitrator... http://www.freshpatents.com/Semiconductor-apparatus-and-buffer-control-circuit-dt20080703ptan20080162746.php Wed, 9 Jul 2008 07:49:35 -0700 A semiconductor apparatus comprises a data processing unit for processing data, a buffer for temporarily storing the data processed by the data processing unit, and a buffer control unit for causing the data stored in the buffer to be burst-transferred to a data storage unit. The buffer control unit allows... http://www.freshpatents.com/Multi-media-kvm-switch-dt20080703ptan20080162747.php Wed, 9 Jul 2008 07:49:35 -0700 A multi-media KVM switch is for providing an output signal to drive a user-interface output device. The multi-media KVM switch comprises an embedded multi-media system, an arbiter and a multiplexer. The embedded multi-media system is enabled as receiving an enabling signal and providing a first device signal. The arbiter is... http://www.freshpatents.com/Efficient-power-management-techniques-for-computer-systems-dt20080703ptan20080162748.php Wed, 9 Jul 2008 07:49:35 -0700 Techniques involving power management techniques in computer systems are disclosed. For instance, an apparatus may include an input output queue (IOQ), an interface coupled to a processor, and a control module. The interface communicates with the processor regarding power states of the processor. The control module may initiate draining the... http://www.freshpatents.com/Low-latency-mechanism-for-data-transfers-between-a-media-controller-and-a-communication-device-dt20080703ptan20080162750.php Wed, 9 Jul 2008 07:49:35 -0700 A mechanism and technique to transfer data between a communication device and media hardware in a computing device. More particularly, an embodiment of the invention uses a quality of service to assure deterministic latencies in direct data transfers between a memory buffer and each of a communication device and an... http://www.freshpatents.com/Method-and-apparatus-for-dynamic-data-buffer-dt20080703ptan20080162749.php Wed, 9 Jul 2008 07:49:35 -0700 A dynamic data buffer method, includes providing a system for accessing a database having a plurality of fields of data potentially used by applications, analyzing an application's structure to identify at least one field of data from the plurality of fields of data in the database used by the application,... http://www.freshpatents.com/Multi-buffer-asynchronous-scheme-for-processing-incoming-information-dt20080703ptan20080162751.php Wed, 9 Jul 2008 07:49:35 -0700 Disclosed is an electronic device featuring a multi buffer scheme for processing incoming signals. For example, two buffers can be used. A processor can read and process stored signals from a first buffer while an incoming data module can concurrently store signals in a second buffer. Once, the processor is... http://www.freshpatents.com/Keyboard-video-mouse-cable-having-indicator-for-indicating-switching-status-dt20080703ptan20080162752.php Wed, 9 Jul 2008 07:49:35 -0700 The present invention discloses a Keyboard-Video-Mouse (KVM) cable capable of indicating at least one switching status of a KVM switch for at least one computer coupled thereto. The KVM cable further comprises a set of transmission lines for transmitting indicating signals from the KVM switch to the indicator. The KVM... http://www.freshpatents.com/Method-for-performing-full-transfer-automation-in-a-usb-controller-dt20080703ptan20080162753.php Wed, 9 Jul 2008 07:49:35 -0700 A USB controller and method of implementing a full transfer automation mode is described. The USB controller may have a host interface module configured to generate hardware logic signals for communication to a backend module having buffer memory. The backend module may be configured to generate hardware logic signals for... http://www.freshpatents.com/Storage-apparatus-and-control-method-dt20080703ptan20080162755.php Wed, 9 Jul 2008 07:49:35 -0700 The interface changeover switch, serving as an external interface, selects any of the USB interface and the E-SATA interface. The conversion LSI reads in a changeover signal of the interface changeover switch from the GP-IO port upon turning power on, and executes signal conversion between the serial ATA interface of... http://www.freshpatents.com/Storage-system-program-and-method-dt20080703ptan20080162754.php Wed, 9 Jul 2008 07:49:35 -0700 Disclosed is a storage system including a unit that requests reconnection to a host after once disconnecting the connection, and a unit that on receipt of a message for reconnection from the host sends to the host a message indicating that connection migration has been made to another storage and... http://www.freshpatents.com/Method-and-apparatus-for-communication-between-universal-serial-bus--usb--host-and-usb-device-dt20080703ptan20080162756.php Wed, 9 Jul 2008 07:49:35 -0700 A method of interfacing between a universal serial bus (USB) host and a USB device. The USB host and the USB device include modules to process packets according to network protocols, instead of USB bus interfaces. Therefore, the USB device can be connected to the USB host even without a... http://www.freshpatents.com/Transactional-flow-management-interrupt-debug-architecture-dt20080703ptan20080162757.php Wed, 9 Jul 2008 07:49:35 -0700 According to some embodiments, a first bus may be monitored, via a first debug gate, the first bus being to exchange data between a first processing system and a second processing system. A second bus may also be monitored, via a second debug gate, the second bus being to exchange... http://www.freshpatents.com/Method-and-apparatus-for-adjusting-the-performance-of-a-synchronous-memory-system-dt20080703ptan20080162759.php Wed, 9 Jul 2008 07:49:35 -0700 A method and apparatus for adjusting the performance of a memory system is provided. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating information from the master device... http://www.freshpatents.com/System-and-method-for-enhancing-i2c-bus-data-rate-dt20080703ptan20080162758.php Wed, 9 Jul 2008 07:49:35 -0700 A system for, and method of, enhancing I2C bus data rate and an electronic assembly including the system or the method. In one embodiment, the system includes: (1) a modulus register associable with a slave device and configured to contain a modulus and (2) data transfer logic associated with the... http://www.freshpatents.com/Efficient-resource-arbitration-dt20080703ptan20080162760.php Wed, 9 Jul 2008 07:49:35 -0700 Resource requests are allocated by storing resource requests in a queue slots in a queue. A token is associated with one of the queue slots. During an arbitration cycle, the queue slot with the token is given the priority to the resource. If the queue slot with the token does... http://www.freshpatents.com/Interrupt-control-circuit-circuit-board-electro-optic-device-and-electronic-apparatus-dt20080703ptan20080162761.php Wed, 9 Jul 2008 07:49:35 -0700 An interrupt control circuit includes: a section that generates an interrupt signal for requesting an interrupt in response to occurrence of a plurality of interrupt causes; a section that generates an interrupt vector signal for indicating a storing destination of an interrupt processing program corresponding any of the plurality of... http://www.freshpatents.com/Interrupt-remapping-based-on-requestor-identification-dt20080703ptan20080162762.php Wed, 9 Jul 2008 07:49:35 -0700 Embodiments of apparatuses, methods, and systems for interrupt remapping based on requestor identification are disclosed. In one embodiment, an apparatus includes look-up logic, and comparison logic. The look-up logic is to look-up an entry associated with an interrupt request in a data structure. The comparison logic is to compare an... http://www.freshpatents.com/Interrupt-mailbox-in-host-memory-dt20080703ptan20080162763.php Wed, 9 Jul 2008 07:49:35 -0700 Embodiments of an interrupt mailbox in host memory are described herein. In an implementation, a device connected to a host writes interrupt data corresponding to an interrupt generated by the device to host memory. Then, the host, when processing the interrupt, accesses the interrupt data from the host memory.... http://www.freshpatents.com/Processing-method-and-processing-device-for-a-hardware-interrupt-dt20080703ptan20080162764.php Wed, 9 Jul 2008 07:49:35 -0700 The present invention discloses a processing device and a processing method for a hardware interrupt, for processing the sharing interrupt. The processing method for the hardware interrupt comprises steps of: after receiving a hardware interrupt, determining whether the hardware interrupt is a sharing interrupt, and if not, sending the interrupt... http://www.freshpatents.com/Method-and-apparatus-for-controlling-connections-of-pc-cards-and-a-passive-card-adapting-card-used-for-connecting-one-of-the-pc-cards-to-the-apparatus-dt20080703ptan20080162765.php Wed, 9 Jul 2008 07:49:35 -0700 A PC card control apparatus includes a PC card connector, a card detector and an interconnection switching circuit. The PC card connector is configured to provide connections for connecting one of a first PC card compliant with specific card standards and a card-adapting card for connecting a second PC card... http://www.freshpatents.com/4x-framer-deframer-module-for-pci-express-and-pci-express-framer-deframer-device-using-the-same-dt20080703ptan20080162767.php Wed, 9 Jul 2008 07:49:35 -0700 Provided is a 4× framer/deframer module for PCI-Express and a framer/deframer device using the same. In the PCI-Express for high-rate data processing, delimiter and pad processing, and 4× framer shifting and arrangement/reverse arrangement for framing/deframing a frame format are performed to achieve a structure that facilitates reconfiguration and expansion, for... http://www.freshpatents.com/Memory-interface-for-volatile-and-non-volatile-memory-devices-dt20080703ptan20080162768.php Wed, 9 Jul 2008 07:49:35 -0700 Accessing data stored in a memory device through an interface, with addressing data on the memory device through at least one address bus, controlling at least data flow to and from the memory device through at least one command bus, and transferring data to and from the memory through at... http://www.freshpatents.com/Signal-techniques-for-bus-interfaces-dt20080703ptan20080162766.php Wed, 9 Jul 2008 07:49:35 -0700 Techniques involving the transfer of signals across interconnection media are disclosed. For instance, an apparatus may include a configuration module and a driver module. The configuration module establishes an operational mode setting from a first operational mode and a second operational mode. The driver module may operate according to this... http://www.freshpatents.com/Systems-and-methods-for-improving-data-transfer-between-devices-dt20080703ptan20080162769.php Wed, 9 Jul 2008 07:49:35 -0700 Systems and methods are disclosed for detecting a first device on a first bus issuing a read request for an amount of data to a second device on a second bus. The systems and methods further include detecting a bridge requesting a first portion of the data from the second... http://www.freshpatents.com/Bus-arbitration-system-dt20080703ptan20080162771.php Wed, 9 Jul 2008 07:49:35 -0700 A circuit arrangement for bus arbitration alters the sequence in which device requests are arbitrated with respect to each other and to a previous arbitration sequence. To this end, an arbiter grants access to a first group of devices according to a predetermined sequence. The arbiter then automatically alters the... http://www.freshpatents.com/Hardware-voting-mechanism-for-arbitrating-scaling-of-shared-voltage-domain-integrated-circuits-processes-and-systems-dt20080703ptan20080162770.php Wed, 9 Jul 2008 07:49:35 -0700 An electronic circuit includes processors (CPU1, CPU2) operable to make respective voltage requests (Vcpu1, Vcpu2), and a power management circuit (1470) having a controllable supply voltage output (VDD1) is coupled to said processors (CPU1, CPU2) and further has a voting circuit (4520) responsive to the voltage requests (Vcpu1, Vcpu2) and... http://www.freshpatents.com/Portable-memory-device-with-auto-play-audio-dt20080703ptan20080162772.php Wed, 9 Jul 2008 07:49:35 -0700 A USB flash memory device is provided which automatically plays pre-recorded audio when the device is inserted into a USB port of a personal computer. The housing of the memory device may be imprinted with promotional information. The pre-recorded audio may include a promotional message, a message relating to a... http://www.freshpatents.com/Apparatus-and-methods-for-multiple-unidirectional-virtual-connections-among-sas-devices-dt20080703ptan20080162773.php Wed, 9 Jul 2008 07:49:35 -0700 Apparatus and methods for enabling multiple, unidirectional, virtual connections between a first SAS device and multiple other SAS devices in a SAS domain. An enhanced first SAS device may be substantially simultaneously coupled to each of two other SAS devices through one or more appropriately enhanced SAS expanders to allow... http://www.freshpatents.com/Interleave-mechanism-for-a-computing-environment-dt20080703ptan20080162774.php Wed, 9 Jul 2008 07:49:35 -0700 Provided is a system to communicate data in a computing environment, comprising an interleaving mechanism operable to interleave data being communicated across the computing environment according to a selected interleaving protocol; and an interleaving instruction set operable on the interleaving mechanism providing operating instructions to the interleaving mechanism in accordance...