http://www.freshpatents.com/Electrical-computers-and-digital-processing-systems--memory-dtnewntc711.php USPTO Class 711 - Electrical computers and digital processing systems: memory en-us Thu, 24 Jul 2008 15:12:42 -0700 1000 Wednesday Thursday Friday Saturday Sunday 141 31 http://www.freshpatents.com/index.php?rss=true http://www.freshpatents.com/images/freshpatentsnav_rss.gif http://www.freshpatents.com/Memory-controller-connectivity-dt20080717ptan20080172515.php Thu, 24 Jul 2008 15:12:42 -0700 A memory controller with an interface for providing a connection to a plurality of memory devices at least one of said plurality of memory devices supporting burst mode data transfers comprises data interface circuitry for connecting to a plurality of separate data buses for communicating data signals between said memory... http://www.freshpatents.com/Multiprocessor-system-and-method-thereof-dt20080717ptan20080172516.php Thu, 24 Jul 2008 15:12:42 -0700 A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory... http://www.freshpatents.com/Flash-memory-module-storage-apparatus-using-flash-memory-module-as-storage-medium-and-address-translation-table-verification-method-for-flash-memory-module-dt20080717ptan20080172523.php Thu, 24 Jul 2008 15:12:42 -0700 A flash memory controller having memory that stores an address translation table for translating between a logical page address and a physical page address in the flash memory chip controls regular mode and low power consumption mode of operating at lower power consumption than in regular mode by halting operation,... http://www.freshpatents.com/Information-processing-apparatus-and-incremental-write-type-file-management-software-dt20080717ptan20080172522.php Thu, 24 Jul 2008 15:12:42 -0700 An information processing apparatus has a common incremental write type file system allowing an incremental write type file access, including an incremental write type file write, to an incremental write type optical recording medium and a non-volatile semiconductor memory device.... http://www.freshpatents.com/Mask-programmable-memory-with-reserved-space-dt20080717ptan20080172517.php Thu, 24 Jul 2008 15:12:42 -0700 The present invention discloses a mask-programmable memory with reserved space (RS-MPM). It is released in a sequence of versions. In the original version, its storage space comprises a reserved space, which does not store any meaningful information. In the later version, the reserved space stores new release. RS-MPM can be... http://www.freshpatents.com/Memory-system-determining-storage-mode-according-to-host-provided-data-information-dt20080717ptan20080172521.php Thu, 24 Jul 2008 15:12:42 -0700 Some embodiments of the present invention provide a memory system including a flash memory including a plurality of memory cells and a memory controller configured to receive data information from a host and to selectively store data in the flash memory in single-bit and multi-bit storage modes responsive to the... http://www.freshpatents.com/Methods-for-supporting-readydrive-and-readyboost-accelerators-in-a-single-flash-memory-storage-device-dt20080717ptan20080172519.php Thu, 24 Jul 2008 15:12:42 -0700 Methods for enhancing the performance of a host system including the steps of: providing an operating system, running on the host system, that supports a ReadyDrive and ReadyBoost accelerator; and providing a flash-memory storage device, which supports both the accelerators, having a single flash-memory module. Preferably, the method further includes... http://www.freshpatents.com/Nonvolatile-memory-devices-including-multiple-user-selectable-program-modes-and-related-methods-of-operation-dt20080717ptan20080172520.php Thu, 24 Jul 2008 15:12:42 -0700 A memory device includes a flash memory, a memory controller, and an MLC mode selector. The flash memory includes at least one memory cell configured to store multi-bit data therein. The MLC mode selector is configured to generate a mode selection signal indicating whether to store single-bit data or multi-bit... http://www.freshpatents.com/Systems-for-supporting-readydrive-and-readyboost-accelerators-in-a-single-flash-memory-storage-device-dt20080717ptan20080172518.php Thu, 24 Jul 2008 15:12:42 -0700 The present invention discloses a flash-memory storage device for implementing both ReadyBoost and ReadyDrive Windows PC accelerators, the device including: a single flash-memory module adapted to be configured as a ReadyBoost accelerator and as a ReadyDrive accelerator; and a controller for controlling the flash-memory module. Preferably, the device further includes:... http://www.freshpatents.com/Systems-and-methods-for-utilizing-an-extended-translation-look-aside-buffer-having-a-hybrid-memory-structure-dt20080717ptan20080172524.php Thu, 24 Jul 2008 15:12:42 -0700 Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual memory addresses corresponding with the physical addresses, the virtual memory... http://www.freshpatents.com/Storage-system-and-method-of-controlling-a-storage-system-dt20080717ptan20080172525.php Thu, 24 Jul 2008 15:12:42 -0700 A storage system includes a plurality of disk drives, and a disk controller for controlling the plurality of disk drives. The plurality of disk drives are configured from a plurality of virtual devices, to which logical devices are allocated. The disk controller apparatus comprises a channel adapter connected to the... http://www.freshpatents.com/Exchange-2-5---to-3-5---redundant-array-of-independent-disks-module-dt20080717ptan20080172527.php Thu, 24 Jul 2008 15:12:42 -0700 A redundant array of independent disks (RAID) module converted from a 2.5-inch specification to a 3.5-inch specification is characterized in that two 2.5-inch SATA hard disks are installed within a standard 3.5-inch SATA RAID module, so as to form a RAID having two hard disks or two stand-alone SATA hard... http://www.freshpatents.com/Method-and-system-for-placement-of-logical-data-stores-to-minimize-request-response-time-dt20080717ptan20080172526.php Thu, 24 Jul 2008 15:12:42 -0700 Logical data stores are placed on storages to minimize store request time. The stores are sorted. A store counter and a storage counter are each set to one. (A), (B), and (C) are repeated until the storage counter exceeds the number of storages within the array. (A) is setting a... http://www.freshpatents.com/Storage-system-dt20080717ptan20080172528.php Thu, 24 Jul 2008 15:12:42 -0700 A disk array includes a drive management unit, which is a program for identifying kinds of disk devices and managing different disk devices separately, and a drive management table for storing information to be utilized by the drive management unit. The disk array further includes a program for managing accumulated... http://www.freshpatents.com/Novel-context-instruction-cache-architecture-for-a-digital-signal-processor-dt20080717ptan20080172529.php Thu, 24 Jul 2008 15:12:42 -0700 Improved thrashing aware and self configuring cache architectures that reduce cache thrashing without increasing cache size or degrading cache hit access time, for a DSP. In one example embodiment, that is accomplished by selectively caching only the instructions having a higher probability of recurrence to considerably reduce cache thrashing.... http://www.freshpatents.com/Apparatus-and-method-for-managing-stacks-for-efficient-memory-usage-dt20080717ptan20080172530.php Thu, 24 Jul 2008 15:12:42 -0700 An apparatus and method for managing stacks for efficient memory usage. The apparatus includes a fault cause analysis unit to recognize a page fault caused by a marking page; a control unit to set the marking page, to request compression of a first stack page depending on whether a page... http://www.freshpatents.com/Data-aware-cache-state-machine-dt20080717ptan20080172531.php Thu, 24 Jul 2008 15:12:42 -0700 Management of a Cache is provided by differentiating data base on attributes associated with the data and reducing storage bottlenecks. The Cache differentiates and manages data using a state machine with a plurality of states. the Cache may use data patterns and statistics to retain frequently used data in the... http://www.freshpatents.com/Apparatus-for-performing-and-coordinating-data-storage-functions-dt20080717ptan20080172532.php Thu, 24 Jul 2008 15:12:42 -0700 A storage processor is constructed on or within an interconnected circuit (IC) chip. The storage processor has a plurality of ports operable to send and/or receive messages to/from storage devices. An output indication circuit is associated with each output port. The indication circuit indicates that data is ready to be... http://www.freshpatents.com/Detector-to-search-for-control-data-dt20080717ptan20080172533.php Thu, 24 Jul 2008 15:12:42 -0700 Implementations related to detecting control data are presented herein. A detector searches for control data in a first set of pre-determined control data, wherein a respective subset of the first set is assigned to a respective logical port and the respective subset is excluded from the first set when searching... http://www.freshpatents.com/Memory-controller-and-method-of-controlling-a-memory-dt20080717ptan20080172534.php Thu, 24 Jul 2008 15:12:42 -0700 A memory controller includes a control circuit configured to provide a control signal, an output interface unit, and a command storage unit coupled to the control circuit and the output interface. The command storage unit is configured to store a plurality of commands, receive the control signal, and provide, in... http://www.freshpatents.com/Buffering-module-set-in-optical-disc-drive-and-related-method-of-buffering-data-dt20080717ptan20080172535.php Thu, 24 Jul 2008 15:12:42 -0700 A method for buffering data when reading an optical disc is disclosed in the present invention. The method includes providing a memory page with a plurality of memory spaces corresponding to a memory space matrix with M rows×N columns, reading data stored in the optical disc to generate a block... http://www.freshpatents.com/Remote-storage-disk-control-device-and-method-for-controlling-the-same-dt20080717ptan20080172537.php Thu, 24 Jul 2008 15:12:42 -0700 A storage device system includes an information processing device, a first storage device equipped with a first storage volume, and a second storage device equipped with a second storage volume. The information processing device and the first storage device are communicatively connected to one another. Also, the first storage device... http://www.freshpatents.com/Storage-system-management-based-on-a-backup-and-recovery-solution-embedded-in-the-storage-system-dt20080717ptan20080172536.php Thu, 24 Jul 2008 15:12:42 -0700 A method and/or a system of storage system management based on a backup and recovery solution embedded in the storage system is disclosed. A method of a storage system includes coordinating with a host system through a backup coordinator module embedded in the host system during at least one of... http://www.freshpatents.com/Page-protection-based-memory-access-barrier-traps-dt20080717ptan20080172538.php Thu, 24 Jul 2008 15:12:42 -0700 A method, apparatus and computer program product for providing page-protection based memory access barrier traps is presented. A value for a user-mode bit (u-bit) is computed for each extant virtual page in an address space, the u-bit indicative that an object on the virtual page is being moved by a... http://www.freshpatents.com/Systems-and-methods-for-memory-migration-dt20080717ptan20080172539.php Thu, 24 Jul 2008 15:12:42 -0700 Systems, methods and media for performing auto-migration of data among a plurality of memory devices are disclosed. In one embodiment, memory access of application program data is monitored for each of one or more application programs. The data may be stored in one or more of a plurality of memory... http://www.freshpatents.com/Asynchronous-data-interface-dt20080717ptan20080172540.php Thu, 24 Jul 2008 15:12:42 -0700 An interface system is disclosed. In one embodiment, the system includes a buffer that receives data from a source in a first clock domain and stores the data to be read by a destination in a second clock domain, wherein the buffer functions in both the first clock domain and... http://www.freshpatents.com/Data-management-apparatus-and-method-dt20080717ptan20080172541.php Thu, 24 Jul 2008 15:12:42 -0700 A data management apparatus and method. The data management apparatus includes an input unit to receive a request to update information included in a predetermined master BAT (block allocation table) block of a plurality of master BAT blocks; and an update unit to record updated information to the predetermined master... http://www.freshpatents.com/Hierarchy-of-a-structure-of-a-volume-dt20080717ptan20080172542.php Thu, 24 Jul 2008 15:12:42 -0700 A method, apparatus and system of a hierarchy of a structure of a volume is disclosed. In one embodiment, a system includes a physical volume, a structure to provide a mapping to a location of a data segment of the physical volume that may include a table having a hierarchy,... http://www.freshpatents.com/Device-method-and-computer-program-product-for-multi-level-address-translation-dt20080717ptan20080172543.php Thu, 24 Jul 2008 15:12:42 -0700 A method for retrieving information from a storage unit, the method includes: receiving, by an input output memory management unit second-level translation information representative of a partition of a storage unit address space; receiving, by a input output memory management unit, a direct memory access request that comprises a consumer... http://www.freshpatents.com/Method-and-apparatus-to-search-for-errors-in-a-translation-look-aside-buffer-dt20080717ptan20080172544.php Thu, 24 Jul 2008 15:12:42 -0700 A method and apparatus for discovering errors in a translation look-aside buffer (TLB). The TLB comprises a content addressable memory (CAM) and a random access memory (RAM). The TLB contains additional logic to check for error when the TLB is not in normal use to translate from a first set... http://www.freshpatents.com/System-and-method-for-accessing-and-displaying-interactive-content-and-advertising-dt20080717ptan20080172545.php Thu, 24 Jul 2008 15:12:42 -0700 System and method for accessing and displaying personal information along with advertisement, software applications, or the like. The system and method include: retrieving from a memory device a unique identifier and a pointer; retrieving a redirect pointer from a pointer table responsive to the retrieved unique identifier and pointer; executing...