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    <title>FreshPatents.com: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) - USPTO Class 712 Patent Applications Update</title> 
    <link>http://www.freshpatents.com/Electrical-computers-and-digital-processing-systems--processing-architectures-and-instruction-processing--e-g--processors--dtnewntc712.php</link> 
    <description>USPTO Class 712 - Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)</description>
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    <lastBuildDate>Wed, 30 Apr 2008 12:40:10 -0700</lastBuildDate> 
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		<item>
  		<title>Two dimensional addressing of a matrix-vector register array</title> 
  		<link>http://www.freshpatents.com/Two-dimensional-addressing-of-a-matrix-vector-register-array-dt20080424ptan20080098200.php</link> 
  		<pubDate>Wed, 30 Apr 2008 12:40:10 -0700</pubDate> 
  		<description>A processor for processing matrix data. The processor includes M independent vector register files which are adapted to collectively store a matrix of L data elements. Each data element has B binary bits. The matrix has N rows and M columns, and L=N*M. Each column has K subcolumns. N&#x2267;2, M&#x2267;2,...</description> 
  	</item>



		<item>
  		<title>Parallel data processing apparatus</title> 
  		<link>http://www.freshpatents.com/Parallel-data-processing-apparatus-dt20080424ptan20080098201.php</link> 
  		<pubDate>Wed, 30 Apr 2008 12:40:10 -0700</pubDate> 
  		<description>A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array. The apparatus is operable to process multiple instructions streams in parallel with one another....</description> 
  	</item>



		<item>
  		<title>Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry havingf fixed, application specific computational elements</title> 
  		<link>http://www.freshpatents.com/Apparatus-method-system-and-executable-module-for-configuration-and-operation-of-adaptive-integrated-circuitry-havingf-fixed-application-specific-computational-elements-dt20080424ptan20080098203.php</link> 
  		<pubDate>Wed, 30 Apr 2008 12:40:10 -0700</pubDate> 
  		<description>The present invention concerns configuration of a new category of integrated circuitry for adaptive computing. The various embodiments provide an executable information module for an adaptive computing engine (ACE) integrated circuit and may include configuration information, operand data, and may also include routing and power control information. The ACE IC...</description> 
  	</item>



		<item>
  		<title>Coupling a general purpose processor to an application specific instruction set processor</title> 
  		<link>http://www.freshpatents.com/Coupling-a-general-purpose-processor-to-an-application-specific-instruction-set-processor-dt20080424ptan20080098202.php</link> 
  		<pubDate>Wed, 30 Apr 2008 12:40:10 -0700</pubDate> 
  		<description>Provides methods, systems and apparatus for coupling a general purpose processor (GPP) to an application specific instruction set processor (ASIP) in such a manner that the GPP can include execute instructions that do not normally comprise part of its instruction set architecture (ISA). The GPP is coupled to the ASIP...</description> 
  	</item>



		<item>
  		<title>Apparatus and methods for stabilization of processors, operating systems and other hardware and/or software configurations</title> 
  		<link>http://www.freshpatents.com/Apparatus-and-methods-for-stabilization-of-processors-operating-systems-and-other-hardware-and-or-software-configurations-dt20080424ptan20080098205.php</link> 
  		<pubDate>Wed, 30 Apr 2008 12:40:10 -0700</pubDate> 
  		<description>Apparatus and methods for converting a processor, having a plurality of states and being operative to execute software operations stored in a memory device, into a self-stabilizing processor, comprising providing self-stabilizing watchdog hardware that, with given timing, interacts with the processor, in accordance with an interaction sequence that includes at...</description> 
  	</item>



		<item>
  		<title>Method and apparatus for improving the efficiency of a processor instruction pipeline</title> 
  		<link>http://www.freshpatents.com/Method-and-apparatus-for-improving-the-efficiency-of-a-processor-instruction-pipeline-dt20080424ptan20080098204.php</link> 
  		<pubDate>Wed, 30 Apr 2008 12:40:10 -0700</pubDate> 
  		<description>A system and method are disclosed which may include providing a processor instruction pipeline having a main line and a branch line; executing at least one wait cycle for at least one wait instruction in said pipeline; and advancing at least selected instructions, that are initially located subsequent to at...</description> 
  	</item>



		<item>
  		<title>Plotting device and plotting method</title> 
  		<link>http://www.freshpatents.com/Plotting-device-and-plotting-method-dt20080424ptan20080098206.php</link> 
  		<pubDate>Wed, 30 Apr 2008 12:40:10 -0700</pubDate> 
  		<description>A reference address generator receives UV coordinate values from a shader, converts the value into a reference address for referring to a texture, and refers to a texture map or an instruction map stored in a texture memory based upon the reference address. The value referred to by the texture...</description> 
  	</item>



		<item>
  		<title>Analyzing diagnostic data generated by multiple threads within an instruction stream</title> 
  		<link>http://www.freshpatents.com/Analyzing-diagnostic-data-generated-by-multiple-threads-within-an-instruction-stream-dt20080424ptan20080098207.php</link> 
  		<pubDate>Wed, 30 Apr 2008 12:40:10 -0700</pubDate> 
  		<description>A diagnostic method for outputting diagnostic data relating to processing of instruction streams stemming from a computer program, at least some of said instructions streams comprising multiple threads is disclosed. The method comprises the steps of: (i) receiving diagnostic data; (ii) reordering said received diagnostic data in dependence upon reordering...</description> 
  	</item>



		<item>
  		<title>Analyzing and transforming a computer program for executing on asymmetric multiprocessing systems</title> 
  		<link>http://www.freshpatents.com/Analyzing-and-transforming-a-computer-program-for-executing-on-asymmetric-multiprocessing-systems-dt20080424ptan20080098208.php</link> 
  		<pubDate>Wed, 30 Apr 2008 12:40:10 -0700</pubDate> 
  		<description>A method is disclosed for transforming a portion of a computer program comprising a list of sequential instructions comprising control code and data processing code and a program separation indicator indicating a point where said sequential instructions may be divided to form separate sections that are capable of being separately...</description> 
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