http://www.freshpatents.com/Electrical-computers-and-digital-processing-systems--processing-architectures-and-instruction-processing--e-g--processors--dtnewntc712.php USPTO Class 712 - Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) en-us Mon, 6 Feb 2012 13:34:45 -0800 1000 Wednesday Thursday Friday Saturday Sunday 141 31 http://www.freshpatents.com/index.php?rss=true http://www.freshpatents.com/images/freshpatentsnav_rss.gif http://www.freshpatents.com/-dt20120202ptan20120030448.php Mon, 6 Feb 2012 13:34:45 -0800 A single instruction multiple data (SIMD) processor having a plurality of processing elements and including: a splitting unit for splitting an address of the read-only parameter data in the data memory into a first part and a second part at a bit position corresponding to the number of the processor... http://www.freshpatents.com/-dt20120202ptan20120030449.php Mon, 6 Feb 2012 13:34:45 -0800 The present disclosure relates to methods and systems for data tag control for quantum dot cellular automata (QCA). An example method includes receiving data, associating a data tag with the data, communicating the data tag along a first wire-like element to a local tag decoder, reading instructions from the data... http://www.freshpatents.com/-dt20120202ptan20120030450.php Mon, 6 Feb 2012 13:34:45 -0800 A method and system for parallel computation of a linear sequential circuit (LSC) based on a state transition matrix is disclosed herein. A multistep state transition matrix and a multistep output generation matrix can be pre-computed and stored in association with the linear sequential circuit. The multiple state transitions and... http://www.freshpatents.com/-dt20120202ptan20120030451.php Mon, 6 Feb 2012 13:34:45 -0800 An Parallel and Long Adaptive Instruction Set Architecture (PALADIN) is provided to optimize packet processing. The Instruction Set Architecture (ISA) includes instructions such as aggregate comparison, comparison OR, comparison AND and bitwise instructions. The ISA also includes dedicated packet processing instructions such as hash, predicate, select, checksum and time to... http://www.freshpatents.com/-dt20120202ptan20120030452.php Mon, 6 Feb 2012 13:34:45 -0800 The present disclosure includes methods, devices, modules, and systems for modifying commands. One device embodiment includes a memory controller including a channel, wherein the channel includes a command queue configured to hold commands, and circuitry configured to modify at least a number of commands in the queue and execute the... http://www.freshpatents.com/-dt20120202ptan20120030453.php Mon, 6 Feb 2012 13:34:45 -0800 A more efficient technique is provided in an information processing apparatus which executes processing using pipelines. An information processing apparatus according to this invention includes a first pipeline, second pipeline, processing unit, and reorder unit. The first pipeline has a plurality of first nodes, and shifts first data held in...