http://www.freshpatents.com/Electrical-computers-and-digital-processing-systems--processing-architectures-and-instruction-processing--e-g--processors--dtnewntc712.php USPTO Class 712 - Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) en-us Tue, 18 Aug 2009 23:39:02 -0700 1000 Wednesday Thursday Friday Saturday Sunday 141 31 http://www.freshpatents.com/index.php?rss=true http://www.freshpatents.com/images/freshpatentsnav_rss.gif http://www.freshpatents.com/Butterfly-physical-chip-floorplan-to-allow-an-ilp-core-polymorphism-pairing-dt20090813ptan20090204787.php Tue, 18 Aug 2009 23:39:02 -0700 Improved techniques for executing instructions in a pipelined manner that may reduce stalls that occur when executing dependent instructions are provided. Stalls may be reduced by utilizing a cascaded arrangement of pipelines with execution units that are delayed with respect to each other. This cascaded delayed arrangement allows dependent instructions... http://www.freshpatents.com/Programmable-pipeline-array-dt20090813ptan20090204788.php Tue, 18 Aug 2009 23:39:02 -0700 Disclosed is an array of programmable data-processing cells configured as a plurality of cross-connected pipelines. An apparatus includes cells capable of performing data-processing functions selectable by a presented instruction. A first set of cells includes an input cell, an output cell, and a series of at least one interior cell... http://www.freshpatents.com/Distributing-parallel-algorithms-of-a-parallel-application-among-compute-nodes-of-an-operational-group-in-a-parallel-computer-dt20090813ptan20090204789.php Tue, 18 Aug 2009 23:39:02 -0700 Methods, apparatus, and products for distributing parallel algorithms of a parallel application among compute nodes of an operational group in a parallel computer are disclosed that include establishing a hardware profile, the hardware profile describing thermal characteristics of each compute node in the operational group; establishing a hardware independent application... http://www.freshpatents.com/Buffer-management-for-real-time-streaming-dt20090813ptan20090204790.php Tue, 18 Aug 2009 23:39:02 -0700 Technologies are described herein for buffer management during real-time streaming. A video frame buffer stores video frames generated by a real-time streaming video capture device. New video frames received from the video capture device are stored in the video frame buffer prior to processing by a video processing pipeline that... http://www.freshpatents.com/Compound-instruction-group-formation-and-execution-dt20090813ptan20090204791.php Tue, 18 Aug 2009 23:39:02 -0700 A method and apparatus for forming compound issue groups containing instructions from multiple cache lines of instructions are provided. By pre-fetching instruction lines containing instructions targeted by a conditional branch statement, if it is predicted that the conditional branch will be taken, a compound issue group may be formed with... http://www.freshpatents.com/Scalar-processor-instruction-level-parallelism--ilp--coupled-pair-morph-mechanism-dt20090813ptan20090204792.php Tue, 18 Aug 2009 23:39:02 -0700 Improved techniques for executing instructions in a pipelined manner that may reduce stalls that occur when executing dependent instructions are provided. Stalls may be reduced by utilizing a cascaded arrangement of pipelines with execution units that are delayed with respect to each other. This cascaded delayed arrangement allows dependent instructions... http://www.freshpatents.com/Raw-hazard-detection-and-resolution-for-implicitly-used-registers-dt20090813ptan20090204793.php Tue, 18 Aug 2009 23:39:02 -0700 The present invention provides a system, apparatus, and method for detecting and resolving read-after-write hazards encountered in processors following the dispatch of instructions requiring one or more implicit reads in a processor.... http://www.freshpatents.com/Methods-computer-program-products-and-systems-for-unifying-program-event-recording-for-branches-and-stores-in-the-same-dataflow-dt20090813ptan20090204794.php Tue, 18 Aug 2009 23:39:02 -0700 The present invention relates to a method for the unification of PER branch and PER store operations within the same dataflow. The method comprises determining a PER range, the PER range comprising a storage area defined by a designated storage starting area and a designated storage ending area, wherein the... http://www.freshpatents.com/Method-and-system-for-automatically-testing-performance-of-applications-run-in-a-distributed-processing-structure-and-corresponding-computer-program-product-dt20090813ptan20090204795.php Tue, 18 Aug 2009 23:39:02 -0700 Performance of applications run on a distributed processing structure including a grid of processing units is automatically tested by: running at least one application on the distributed processing structure; loading the application with processing workload to thereby produce processing workload on the distributed processing structure; sensing the operating status of... http://www.freshpatents.com/Method-system-and-computer-program-product-for-verifying-address-generation-interlocks-and-bypasses-dt20090813ptan20090204796.php Tue, 18 Aug 2009 23:39:02 -0700 Method, system and computer program product for verifying the address generation, address generation, interlocks, and address generation bypassing controls in a CPU. An exemplary embodiment includes a verification method in a processor, the method including propagating a first set general purpose register values fern a first instruction to a second... http://www.freshpatents.com/Method-and-system-for-mitigating-lookahead-branch-prediction-latency-with-branch-presence-prediction-at-the-time-of-instruction-fetching-dt20090813ptan20090204797.php Tue, 18 Aug 2009 23:39:02 -0700 System and method for mitigating lookahead branch prediction latency with branch presence prediction at the time of instruction fetching. An exemplary embodiment includes a method for mitigating lookahead branch prediction latency, the method including receiving an instruction address in an instruction cache for fetching instructions in the microprocessor pipeline, receiving... http://www.freshpatents.com/Method-and-system-for-reducing-branch-prediction-latency-using-a-branch-target-buffer-with-most-recently-used-column-prediction-dt20090813ptan20090204799.php Tue, 18 Aug 2009 23:39:02 -0700 System and method for reducing branch prediction latency using a branch target buffer with most recently used column prediction. An exemplary embodiment includes a method for reducing branch prediction latency, the method including reading most-recently-used information from a most-recently-used table associated with the branch target buffer where each most-recently-used entry... http://www.freshpatents.com/Simplified-implementation-of-branch-target-preloading-dt20090813ptan20090204798.php Tue, 18 Aug 2009 23:39:02 -0700 A system for using complex branch execution hardware and a hardware based Multiplex (MUX) to multiplex a fetch address of a future branch and a branch fetch address to one index hash value used to index a branch target prediction table for execution by a processor core, to reduce branch... http://www.freshpatents.com/Microprocessor-with-microarchitecture-for-efficiently-executing-read-modify-write-memory-operand-instructions-dt20090813ptan20090204800.php Tue, 18 Aug 2009 23:39:02 -0700 The microprocessor includes an instruction translator that translates a macroinstruction of a macroinstruction set in its macroarchitecture into exactly three microinstructions to perform a read/modify/write operation on a memory operand. The first microinstruction instructs the microprocessor to load the memory operand into the microprocessor from a memory location and to...