http://www.freshpatents.com/Electronic-digital-logic-circuitry-dtnewntc326.php USPTO Class 326 - Electronic digital logic circuitry en-us Thu, 24 Jul 2008 15:01:29 -0700 1000 Wednesday Thursday Friday Saturday Sunday 141 31 http://www.freshpatents.com/index.php?rss=true http://www.freshpatents.com/images/freshpatentsnav_rss.gif http://www.freshpatents.com/Integrated-circuit-with-anti-counterfeiting-measures-dt20080717ptan20080169833.php Thu, 24 Jul 2008 15:01:29 -0700 An anti-counterfeiting circuit that is incorporated into an authentic integrated circuit (IC) design, which induces a random failure in a counterfeited IC when the counterfeit IC is manufactured from a reverse-engineered authentic IC. The anti-counterfeiting circuit uses two signals of differing frequencies, which activate a disrupt signal when the two... http://www.freshpatents.com/Signal-isolators-using-micro-transformers-dt20080717ptan20080169834.php Thu, 24 Jul 2008 15:01:29 -0700 A logic signal isolator comprising a transformer having a primary winding and a secondary winding; a transmitter circuit which drives said primary winding in response to a received logic signal, such that in response to a first type of edge in the logic signal, a signal of a first predetermined... http://www.freshpatents.com/Semiconductor-integrated-circuit-apparatus-dt20080717ptan20080169835.php Thu, 24 Jul 2008 15:01:29 -0700 A semiconductor integrated circuit apparatus relates to a structured ASIC that wires functional cells in a common wiring layer, which is not dependent on a user circuit and common to several sorts, and a customized layer provided over the common wiring layer to form the user circuit. In the semiconductor... http://www.freshpatents.com/Configuration-random-access-memory-dt20080717ptan20080169836.php Thu, 24 Jul 2008 15:01:29 -0700 Integrated circuits such as programmable logic device integrated circuits are provided that have configuration random-access memory elements. The configuration random-access memory elements are loaded with configuration data to customize programmable logic on the integrated circuits. Each memory element has a capacitor that stores data for that memory element. A pair... http://www.freshpatents.com/Current-control-mechanism-for-dynamic-logic-keeper-circuits-in-an-integrated-circuit-and-method-of-regulating-same-dt20080717ptan20080169837.php Thu, 24 Jul 2008 15:01:29 -0700 An integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control gate voltage, global control... http://www.freshpatents.com/Current-mode-circuitry-to-modulate-a-common-mode-voltage-dt20080717ptan20080169838.php Thu, 24 Jul 2008 15:01:29 -0700 In some embodiments, a chip includes transmitters to transmit differential signals on conductors; and current mode circuitry to selectively modulate a common mode voltage of the differential signals to communicate data. In other embodiments, a system includes a first chip to transmit first and second differential signals on conductors, and... http://www.freshpatents.com/Structure-for-a-current-control-mechanism-for-dynamic-logic-keeper-circuits-dt20080717ptan20080169839.php Thu, 24 Jul 2008 15:01:29 -0700 A design structure for an integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control... http://www.freshpatents.com/Semiconductor-device-having-a-pseudo-power-supply-wiring-dt20080717ptan20080169840.php Thu, 24 Jul 2008 15:01:29 -0700 A semiconductor device including an AND-NOR composite gate of which AND unit is supplied with input signals IN and VDD and NOR unit is supplied with an inverted signal EB of an enable signal E, and an AND-NOR composite gate of which AND unit is supplied with an input signal... http://www.freshpatents.com/Design-structure-to-reduce-power-consumption-within-a-clock-gated-synchronous-circuit-and-clock-gated-synchronous-circuit-dt20080717ptan20080169842.php Thu, 24 Jul 2008 15:01:29 -0700 A design structure to reduce power consumption within a clock gated synchronous circuit, said synchronous circuit comprising at least two successive stages, wherein each stage if activated propagates a data signal cycle by cycle to a succeeding stage the two successive stages comprising at least a control register, a data... http://www.freshpatents.com/Method-to-reduce-power-consumption-within-a-clock-gated-synchronous-circuit-and-clock-gated-synchronous-circuit-dt20080717ptan20080169841.php Thu, 24 Jul 2008 15:01:29 -0700 propagating the data signal and the local clock activation signal synchronously cycle by cycle from a particular stage to a succeeding stage whenever a local clock activation signal at the particular stage by derivation from the clock activation signal or by propagation through the synchronous circuit changes its value between...