http://www.freshpatents.com/Error-detection-correction-and-fault-detection-recovery-dtnewntc714.php USPTO Class 714 - Error detection/correction and fault detection/recovery en-us Mon, 20 May 2013 13:47:07 -0700 1000 Wednesday Thursday Friday Saturday Sunday 141 31 http://www.freshpatents.com/index.php?rss=true http://www.freshpatents.com/images/freshpatentsnav_rss.gif http://www.freshpatents.com/-dt20130516ptan20130124908.php Mon, 20 May 2013 13:47:07 -0700 Systems and methods for automatic repair, replacement, and/or configuration of various network devices within a communications network are disclosed. The system may receive indication of a failed network device and automatically perform diagnostic on the network device to determine any problems associated with the hardware and/or software components within the... http://www.freshpatents.com/-dt20130516ptan20130124909.php Mon, 20 May 2013 13:47:07 -0700 A computer-implemented method, a computerized system and a product for providing a cluster of replicated servers. The method performed by a computerized server in a cluster of servers, wherein the cluster of servers are executing replicated instances of an application, wherein the replicated instances are configured to perform the same... http://www.freshpatents.com/-dt20130516ptan20130124910.php Mon, 20 May 2013 13:47:07 -0700 A system and method can provide fault tolerance in a middleware machine environment. A subnet manager can determine whether there is a path record change when a fault occurs in the middleware machine environment. Furthermore, the subnet manager can signal a dynamic reconfiguration event to at least one host in... http://www.freshpatents.com/-dt20130516ptan20130124913.php Mon, 20 May 2013 13:47:07 -0700 A management device includes a memory and a processor coupled to the memory. The processor executes a process including monitoring an operating state of a target device to be managed as a node of a network to be managed, moving a process executed by the target device to another node... http://www.freshpatents.com/-dt20130516ptan20130124911.php Mon, 20 May 2013 13:47:07 -0700 A first component, executing in a first data processing system, receives, over a data communication network using a first adapter, a first diagnostic heartbeat packet from a second adapter in a second data processing system. The first heartbeat packet comprises a header, a set of heartbeat parameters, and a set... http://www.freshpatents.com/-dt20130516ptan20130124912.php Mon, 20 May 2013 13:47:07 -0700 A first component, executing using a processor and a memory in a first data processing system, receives a diagnostic heartbeat packet from a second component executing in a second data processing system, wherein the diagnostic heartbeat packet is a packet comprising a header, a set of heartbeat parameters, and a... http://www.freshpatents.com/-dt20130516ptan20130124914.php Mon, 20 May 2013 13:47:07 -0700 Embodiments of the present invention disclose a method and a device for detecting data reliability, which belong to the field of computer technologies. The method includes: dividing source data into multiple source data blocks; establishing a corresponding duplicate data block for each source data block, where the duplicate data block... http://www.freshpatents.com/-dt20130516ptan20130124917.php Mon, 20 May 2013 13:47:07 -0700 A method and system for recovering from stack-overflow or stack-underflow faults without restarting software or hardware. At every task switch operation in an application program, a portion of the memory stack is copied to a backup location, so that portion of the stack can be restored if it is subsequently... http://www.freshpatents.com/-dt20130516ptan20130124915.php Mon, 20 May 2013 13:47:07 -0700 A remote copy system includes a first storage device performing data transmission/reception with a host computer, a second storage device receiving data from the first storage device, and a third storage device receiving data from the second storage device. The first storage device includes a logical volume, the second storage... http://www.freshpatents.com/-dt20130516ptan20130124916.php Mon, 20 May 2013 13:47:07 -0700 A plurality of data centers each having a plurality of servers. When there is a failure on a data center, the load for the failed portion of the data center is distributed over all the remaining servers locally, or remotely, based on the magnitude of the failure.... http://www.freshpatents.com/-dt20130516ptan20130124918.php Mon, 20 May 2013 13:47:07 -0700 A semiconductor device includes a plurality of processors and a spare processor configured to perform respective processing functions. A plurality of first switches is located at respective inputs of the plurality of processors. Each of the plurality of first switches is configured to selectively provide an input signal to a... http://www.freshpatents.com/-dt20130516ptan20130124919.php Mon, 20 May 2013 13:47:07 -0700 A system and method for remote testing of enterprise software applications (ESA) allows one or more testers to remotely access an ESA and remotely test the ESA. In at least one embodiment, the ESA resides in a testing platform that includes one more computers that are provisioned for testing. “Provisioning”... http://www.freshpatents.com/-dt20130516ptan20130124920.php Mon, 20 May 2013 13:47:07 -0700 A computer-implemented method and apparatus, comprising: having a plurality of processing entities operating substantially concurrently in a computerized platform enabling transaction operations, wherein the plurality of processing entities comprise two or more entities adapted to store values, and one or more entity adapted to load values, wherein each writing entity... http://www.freshpatents.com/-dt20130516ptan20130124921.php Mon, 20 May 2013 13:47:07 -0700 A method and device for predicting faults in a distributed heterogeneous IT system (100), the method comprising: creating a local checkpoint (19) in an explorer node (10) of said system (100), said local checkpoint (19) reflecting the state of said explorer node (10); running a path exploration engine (14) on... http://www.freshpatents.com/-dt20130516ptan20130124923.php Mon, 20 May 2013 13:47:07 -0700 A device detects and diagnoses correlated anomalies of a network. The device includes an anomaly detection module receiving a first data stream including an event-series related to the network. The anomaly detection module executes at least one algorithm to detect a potential anomaly in the event-series. The device further includes... http://www.freshpatents.com/-dt20130516ptan20130124922.php Mon, 20 May 2013 13:47:07 -0700 A method of providing synchronization and integrity checking in a high integrity processing system having at least two redundant processing lanes, with each lane having an application processor, with the application processors running the same application software in a non-lockstep configuration, and outputting transactions requiring access to an addressable space.... http://www.freshpatents.com/-dt20130516ptan20130124924.php Mon, 20 May 2013 13:47:07 -0700 Main functional units of a program analyzing system that analyzes a program while adjusting a time passage speed of a program performance circumstance includes four functional units, that is, an analysis management unit, a sample performing unit, an activity recording unit, and an activity analyzing unit. The analysis management unit... http://www.freshpatents.com/-dt20130516ptan20130124925.php Mon, 20 May 2013 13:47:07 -0700 A method and an apparatus for checking a main memory of a processor, which includes a cache memory and a plurality of registers. Before the memory test is carried out, a boot-up sequence which may be running at that time is interrupted, temporary data required for the memory test is... http://www.freshpatents.com/-dt20130516ptan20130124926.php Mon, 20 May 2013 13:47:07 -0700 A system and computer program product for system care for a computing device. In one embodiment, a process includes analyzing one or more software and hardware components of the computing device by a system care program of the computing device, analyzing system health of the computing device based on the... http://www.freshpatents.com/-dt20130516ptan20130124928.php Mon, 20 May 2013 13:47:07 -0700 One or more non-transitory computer-readable media having stored thereon program instructions to facilitate the display of multiple errors is provided. The program instructions, when executed by a computing system, direct the computing system to at least initiate display of a graphical view of an industrial automation environment. The program instructions... http://www.freshpatents.com/-dt20130516ptan20130124927.php Mon, 20 May 2013 13:47:07 -0700 A method for providing corrections for semantic errors in a process model can be implemented on a computer. The method can include identifying a change in the process model, the process model including one or more process model elements. The method can also include identifying one or more constraint violations... http://www.freshpatents.com/-dt20130516ptan20130124929.php Mon, 20 May 2013 13:47:07 -0700 The data transfer control device of the present invention is capable of improving data transfer efficiency while discarding error data, a DMA parameter storing control unit (1112) temporarily stores parameters to a store resource; a data processing unit (1201) performs error detection processing for data that is transferred; a DMA... http://www.freshpatents.com/-dt20130516ptan20130124930.php Mon, 20 May 2013 13:47:07 -0700 Provided are techniques for receiving a packet transmitted in conjunction with a security association associated with Internet Protocol Security (IPSec); determining, based upon the security Association that the packet is faulty; incrementing a count corresponding to previous faulty packets received; determining that the count exceeds a threshold; and disabling IPSec... http://www.freshpatents.com/-dt20130516ptan20130124932.php Mon, 20 May 2013 13:47:07 -0700 A Solid-State Disk (SSD) Manufacturing Self Test (MST) capability enables an SSD manufacturer to generate and load tests onto SSDs, run the tests, and gather results. The SSDs self execute the loaded tests when powered up. The self executing is while coupled to a host that loaded the tests or... http://www.freshpatents.com/-dt20130516ptan20130124931.php Mon, 20 May 2013 13:47:07 -0700 In one aspect, the present disclosure provides a storage device for accounting for transmission errors to improve a usable life span of memory blocks. In some embodiments, the storage device includes: a memory array including a plurality of memory blocks; and a memory controller in communication with the memory array... http://www.freshpatents.com/-dt20130516ptan20130124933.php Mon, 20 May 2013 13:47:07 -0700 A relatively small amount of programmable logic may be included in a mostly ASIC device such that the programmable logic can be used as a substitute for a fault-infected ASIC block. This substitution may occur permanently or temporarily. When an ASIC block is temporarily substituted, faulty outputs of the ASIC... http://www.freshpatents.com/-dt20130516ptan20130124934.php Mon, 20 May 2013 13:47:07 -0700 Apparatus and techniques for performing JTAG testing on production devices and systems through industry standard interfaces. The devices employ processors configured to receive packetized test input data from a tester over a standard communication interface such as a USB or Ethernet port and perform associated testing operations defined by the... http://www.freshpatents.com/-dt20130516ptan20130124935.php Mon, 20 May 2013 13:47:07 -0700 This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a... http://www.freshpatents.com/-dt20130516ptan20130124936.php Mon, 20 May 2013 13:47:07 -0700 An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response... http://www.freshpatents.com/-dt20130516ptan20130124937.php Mon, 20 May 2013 13:47:07 -0700 A method for transmitting data in a second device that performs a Device-to-Device (D2D) service is provided. The method includes determining cooperative communication, if a value indicating a channel condition between a first device and a third device is less than or equal to a predetermined threshold, overhearing data transmitted... http://www.freshpatents.com/-dt20130516ptan20130124938.php Mon, 20 May 2013 13:47:07 -0700 An apparatus and method are provided for transmitting and receiving a quasi-cyclic Low Density Parity Check (LDPC) code in a multimedia communication system. In the method, a signal transmission apparatus generates a quasi-cyclic LDPC code, and transmits the quasi-cyclic LDPC code to a signal reception apparatus. The quasi-cyclic LDPC code... http://www.freshpatents.com/-dt20130516ptan20130124939.php Mon, 20 May 2013 13:47:07 -0700 A method for forming a bit sequence having a number of M bits from a bit sequence having a number of N bits, wherein M/2<N<M, involves extending said bit sequence by M-N bit positions, segmenting said extended bit sequence into at least two blocks with different numbers of bit positions... http://www.freshpatents.com/-dt20130516ptan20130124940.php Mon, 20 May 2013 13:47:07 -0700 A memory controller is disclosed, having a memory access circuit and an LDPC decoding circuit. The memory access circuit reads the hard information of a first code word and a second code word from a memory device. The LDPC decoding circuit decodes the first code word according to the hard... http://www.freshpatents.com/-dt20130516ptan20130124941.php Mon, 20 May 2013 13:47:07 -0700 Disclosed are a semiconductor memory device, and a method of driving the same, and a cyclic redundancy check code generating circuit capable of performing cyclic redundancy check. A semiconductor memory device according to an aspect of the present invention includes a memory cell array, a data processing unit receiving data... http://www.freshpatents.com/-dt20130516ptan20130124942.php Mon, 20 May 2013 13:47:07 -0700 A data storage system includes a memory circuit and a control circuit. The control circuit is operable to receive data bits provided for storage in memory cells of the memory circuit. The control circuit is operable to compare each of the data bits provided for storage in a corresponding one... http://www.freshpatents.com/-dt20130516ptan20130124943.php Mon, 20 May 2013 13:47:07 -0700 A data storage system includes a memory circuit and a control circuit. The control circuit is operable to receive data bits provided for storage in memory cells of the memory circuit. The control circuit is operable to compare each of the data bits provided for storage in a corresponding one... http://www.freshpatents.com/-dt20130516ptan20130124945.php Mon, 20 May 2013 13:47:07 -0700 The subject technology includes adjusting an error correcting code rate in a solid-state drive. A first plurality of memory operations are performed on a flash memory device of the solid-state drive using a first code rate. During operation of the drive, a controller monitors an operating condition associated with one... http://www.freshpatents.com/-dt20130516ptan20130124944.php Mon, 20 May 2013 13:47:07 -0700 A nonvolatile memory device comprises a memory controller having a memory cell status estimator that generates status estimation information indicating the status of a memory cell based on status register data, a coupling group index selector configured to generate a select signal for selecting a page and coupling group index... http://www.freshpatents.com/-dt20130516ptan20130124946.php Mon, 20 May 2013 13:47:07 -0700 A method and system is disclosed for operating a NAND memory device. The NAND memory device is operated by transmitting serial peripheral interface signals from a host to a NAND memory device, whereby the signals are communicated to a NAND memory in the NAND memory device without modifying the signals... http://www.freshpatents.com/-dt20130516ptan20130124947.php Mon, 20 May 2013 13:47:07 -0700 Techniques are provided for decoding tail-biting convolutional codes by using information within the received data stream that traditionally has not been used or been available to the convolutional decoder, e.g., cyclic redundancy check (CRC) and bit information known by both the transmitter and receiver. Further, a single parallel trace-back is... http://www.freshpatents.com/-dt20130516ptan20130124948.php Mon, 20 May 2013 13:47:07 -0700 This invention relates to methods for obtaining a bin number of path metrics. When performing such methods, a histogram is provided, which composes a bin number of values, a maximum value and a tail region left or right of the maximum value. A bin number of path metrics is obtained... http://www.freshpatents.com/-dt20130516ptan20130124949.php Mon, 20 May 2013 13:47:07 -0700 Various embodiments of the present invention provide circuits, systems and methods for data processing. For example, a data processing system is disclosed that includes: a data detector circuit, a filter circuit, a gain error generation circuit, and a multiplier circuit. The data detector circuit is operable to apply a data... http://www.freshpatents.com/-dt20130516ptan20130124950.php Mon, 20 May 2013 13:47:07 -0700 Various embodiments of the present invention provide apparatuses and methods for encoding and decoding data....