http://www.freshpatents.com/Semiconductor-device-manufacturing--process-dtnewntc438.php USPTO Class 438 - Semiconductor device manufacturing: process en-us Wed, 30 Apr 2008 12:35:01 -0700 1000 Wednesday Thursday Friday Saturday Sunday 141 31 http://www.freshpatents.com/index.php?rss=true http://www.freshpatents.com/images/freshpatentsnav_rss.gif http://www.freshpatents.com/Magnetic-tunnel-junction-memory-and-method-with-etch-stop-layer-dt20080424ptan20080096290.php Wed, 30 Apr 2008 12:35:01 -0700 Methods and apparatus are provided for magnetoresistive memories employing magnetic tunnel junction (MTJ). The apparatus comprises a MTJ (61, 231), first (60, 220) and second (66, 236) electrodes coupled, respectively, to first (62, 232) and second (64, 234) magnetic layers of the MTJ (61, 231), first (54, 204) and second... http://www.freshpatents.com/Method-for-measuring-interface-traps-in-thin-gate-oxide-mosfets-dt20080424ptan20080096292.php Wed, 30 Apr 2008 12:35:01 -0700 A method for measuring interface traps in a MOSFET, comprising measuring charge pumping current of a pulse wave form for various frequencies over a predetermined frequency range, creating plotted points of the measured charge pumping current versus the predetermined frequency range, determining the total number of interface traps participating in... http://www.freshpatents.com/Integrated-circuit-structure-display-module-and-inspection-method-thereof-dt20080424ptan20080096294.php Wed, 30 Apr 2008 12:35:01 -0700 An integrated circuit structure has an IC chip, at least a functional bump, and at least a dummy bump positioned on a joint surface of the IC chip. A terminal surface of the dummy bump is different in appearance from a terminal surface of the functional bump, which improves an... http://www.freshpatents.com/Method-of-manufacturing-a-semiconductor-integrated-circuit-device-dt20080424ptan20080096295.php Wed, 30 Apr 2008 12:35:01 -0700 A technique of manufacturing a semiconductor integrated circuit device is provided for reducing the possibility of attachment of foreign matter to a membrane probe when performing probe inspection using the membrane probe formed by the manufacturing technique. A pressing member for pressing a membrane sheet includes a pressing pin receiving... http://www.freshpatents.com/Electrical-contacts-for-a-semiconductor-light-emitting-apparatus-dt20080424ptan20080096297.php Wed, 30 Apr 2008 12:35:01 -0700 A process for forming electrical contacts for a semiconductor light emitting apparatus is disclosed. The light emitting apparatus has a first layer of first conductivity type, an active layer for generating light overlying the first layer, and a second layer of second conductivity type overlying the active layer. The process... http://www.freshpatents.com/Micro-electro-mechanical-system-dt20080424ptan20080096301.php Wed, 30 Apr 2008 12:35:01 -0700 Embodiments of a micro electro mechanical system are disclosed.... http://www.freshpatents.com/Semiconductor-device-and-method-for-forming-the-same-dt20080424ptan20080096306.php Wed, 30 Apr 2008 12:35:01 -0700 A memory device includes an insulating layer formed over a substrate, a gate formed over the insulating layer, and charge storage elements disposed over the insulating layer. The charge storage elements are separated from each other and are electrically insulated, and each of the charge storage elements is capable of... http://www.freshpatents.com/Method-for-forming-semiconductor-device-and-method-for-forming-photovoltaic-device-dt20080424ptan20080096291.php Wed, 30 Apr 2008 12:35:01 -0700 A method for forming a semiconductor device including a semiconductor layer, formed of a silicon-based deposited film containing crystals by plasma-enhanced CVD, includes the steps of applying a bias voltage between a high-frequency electrode and a substrate with the high-frequency electrode being negative when the semiconductor layer is formed; detecting... http://www.freshpatents.com/Method-and-apparatus-for-evaluation-and-improvement-of-mechanical-and-thermal-properties-of-cnt-cnf-arrays-dt20080424ptan20080096293.php Wed, 30 Apr 2008 12:35:01 -0700 A method and apparatus for the evaluation and improvement of the mechanical and thermal properties of carbon-nanotube (CNT) and carbon nanofiber (CNF) arrays grown on a substrate is disclosed. The Young's modulus of a CNT/CNF material is measured by applying an axial compressive force on the CNT/CNF array and measuring... http://www.freshpatents.com/Ink-jet-printhead-and-manufacturing-method-thereof-dt20080424ptan20080096296.php Wed, 30 Apr 2008 12:35:01 -0700 An ink-jet printhead and a manufacturing method thereof include a substrate on which a space portion is formed, a passage plate installed on the substrate in which an ink chamber is formed to store ink, a nozzle plate installed at a top surface of the passage plate in which a... http://www.freshpatents.com/Self-forming-microlenses-for-vcsel-arrays-dt20080424ptan20080096298.php Wed, 30 Apr 2008 12:35:01 -0700 A Vertical Cavity Surface Emitting Laser (VCSEL) assembly including a VCSEL structure having a light-emitting region located on its surface, a relatively wettable region of a surface modifier coating formed over the light emitting region, and a microlens formed on the relatively wettable region. A relatively non-wettable region of the... http://www.freshpatents.com/Liquid-crystal-display-device-and-fabricating-method-thereof-dt20080424ptan20080096299.php Wed, 30 Apr 2008 12:35:01 -0700 A method for fabricating a liquid crystal display (LCD) device comprises forming an active pattern and a data line on a substrate, the active pattern including a source, a drain, and a channel regions; a first insulation film on a portion of the substrate; forming a gate electrode in a... http://www.freshpatents.com/Manufacturing-method-of-liquid-crystal-display-panel-dt20080424ptan20080096300.php Wed, 30 Apr 2008 12:35:01 -0700 A liquid crystal display panel and a manufacturing method thereof are provided. The liquid crystal display panel comprises a color filter substrate and a thin film transistor array substrate arranged in parallel and a liquid crystal layer between the substrates. In addition, several spacers are disposed on a black matrix... http://www.freshpatents.com/Photodiode-with-ultra-shallow-junction-for-high-quantum-efficiency-cmos-image-sensor-and-method-of-formation-dt20080424ptan20080096302.php Wed, 30 Apr 2008 12:35:01 -0700 A pinned photodiode with an ultra-shallow highly-doped surface layer of a first conductivity type and a method of formation are disclosed. The ultra-shallow highly-doped surface latter has a thickness of about 100 Angstroms to about 500 Angstroms and a dopant concentration of about 5×1017 atoms per cm3 to about 1×1019... http://www.freshpatents.com/Fabrication-method-of-image-sensing-device-dt20080424ptan20080096303.php Wed, 30 Apr 2008 12:35:01 -0700 An image sensing device includes a substrate with a photo sensing and a transistor regions, a photo diode, a transistor, a dielectric layer, a metal interconnect, a metal conductive line, a conformal passivation layer, a color filter, a lens planar layer, and a microlens. The photo diode is in the... http://www.freshpatents.com/Photodiode-array-and-method-for-making-thereof-dt20080424ptan20080096304.php Wed, 30 Apr 2008 12:35:01 -0700 Disclosed is a photodiode array comprising a semiconductor substrate; a plurality of photodiodes formed on the semiconductor substrate; and crystal fused regions losing crystallinity by fusing a semiconductor material of the photodiodes between the plurality of photodiodes.... http://www.freshpatents.com/Method-for-forming-deposited-film-and-photovoltaic-element-dt20080424ptan20080096305.php Wed, 30 Apr 2008 12:35:01 -0700 A method for forming a deposited film containing microcrystalline silicon on a moving substrate by plasma-enhanced CVD includes forming a deposited film containing microcrystalline silicon on a moving substrate by plasma-enhanced CVD under conditions such that when a deposited film having a thickness of 300 nm or more is formed... http://www.freshpatents.com/Method-and-apparatus-for-controlling-composition-profile-of-copper-indium-gallium-chalcogenide-layers-dt20080424ptan20080096307.php Wed, 30 Apr 2008 12:35:01 -0700 The present invention relates to method and apparatus for preparing thin films of semiconductor films for radiation detector and photovoltaic applications. In one aspect, the present invention is directed to a method of forming a Cu(In,Ga)(S,Se)2 layer with substantially uniform Ga distribution. In a particular aspect, the method includes depositing... http://www.freshpatents.com/Methods-for-coupling-diamond-structures-to-photonic-devices-dt20080424ptan20080096308.php Wed, 30 Apr 2008 12:35:01 -0700 Various embodiments of the present invention are directed to methods for coupling semiconductor-based photonic devices to diamond. In one embodiment of the present invention, a method for coupling a photonic device with a diamond structure comprises embedding the diamond structure in a first substrate, where the first substrate comprises a... http://www.freshpatents.com/Semiconductor-on-diamond-devices-and-associated-methods-dt20080424ptan20080096309.php Wed, 30 Apr 2008 12:35:01 -0700 Semiconductor-on-diamond devices and methods for making such devices are provided. One such method may include depositing a semiconductor layer on a semiconductor substrate, depositing an adynamic diamond layer on the semiconductor layer opposite the semiconductor substrate, and coupling a support substrate to the adynamic diamond layer opposite the semiconductor layer... http://www.freshpatents.com/Apparatus-and-method-for-connecting-components-dt20080424ptan20080096311.php Wed, 30 Apr 2008 12:35:01 -0700 An apparatus for connecting at least two components contains a lower die and an upper die. The lower die has the components which are to be connected, with the first component supporting the at least second component with an at least partial overlap relative to the first component. The lower... http://www.freshpatents.com/Embedded-capacitors-for-reducing-package-cracking-dt20080424ptan20080096310.php Wed, 30 Apr 2008 12:35:01 -0700 A linear coefficient of thermal expansion (CTE) mismatch between two materials, such as between a microelectronic die and a mounting substrate, may induce stress at the interface of the materials. The temperature changes present during the process of attaching a die to a mounting substrate can cause cracking and failure... http://www.freshpatents.com/Low-profile-ball-grid-array--bga--package-with-exposed-die-and-method-of-making-same-dt20080424ptan20080096312.php Wed, 30 Apr 2008 12:35:01 -0700 Methods and apparatuses for improved thermal, electrical and/or mechanical performance in integrated circuit (IC) packages are described. An IC circuit package comprises a substrate having a central opening. An IC die, resides within the opening in the substrate. Wirebonds couples a plurality of bond pads on a top surface of... http://www.freshpatents.com/Methods-for-depositing-releasing-and-packaging-micro-electromechanical-devices-on-wafer-substrates-dt20080424ptan20080096313.php Wed, 30 Apr 2008 12:35:01 -0700 A projection system, a spatial light modulator, and a method for forming a MEMS device is disclosed. The spatial light modulator can have two substrates bonded together with one of the substrates comprising a micromirror array. The two substrates can be bonded at the wafer level after depositing a getter... http://www.freshpatents.com/Ball-grid-array-package-and-method-thereof-dt20080424ptan20080096314.php Wed, 30 Apr 2008 12:35:01 -0700 A ball grid array package includes a substrate, a chip, a plurality of pads, a solder mask, a plurality of partitioning walls, and a plurality of solder balls. The substrate has an upper surface and a lower surface opposite to the upper surface. The chip is disposed on the upper... http://www.freshpatents.com/Stacked-chip-package-and-method-for-forming-the-same-dt20080424ptan20080096315.php Wed, 30 Apr 2008 12:35:01 -0700 Provided is a stacked chip package and a method for forming the same. A spacer is formed on a side of an upper chip. A conductive line is formed on the spacer to electrically connect upper and lower chips. The reliability of the stacked chip package is improved because wire... http://www.freshpatents.com/Stacked-die-in-die-bga-package-dt20080424ptan20080096316.php Wed, 30 Apr 2008 12:35:01 -0700 Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.... http://www.freshpatents.com/Method-for-producing-portable-memory-devices-dt20080424ptan20080096317.php Wed, 30 Apr 2008 12:35:01 -0700 Improved techniques to produce integrated circuit products are disclosed. The improved techniques permit smaller and less costly production of integrated circuit products. One aspect of the invention concerns covering test contacts (e.g., test pins) provided with the integrated circuit products using printed ink. Once covered with the ink, the test... http://www.freshpatents.com/Method-of-connecting-carrier-tapes-and-tcp-mounting-apparatus-used-therefor-dt20080424ptan20080096318.php Wed, 30 Apr 2008 12:35:01 -0700 A method of connecting carrier tapes in the TCP mounting apparatus is provided, which makes it surer to form an interconnection between the end portion of a current carrier tape and the beginning portion of a new carrier tape, and which is easy to be carried out. The end portion... http://www.freshpatents.com/Sawn-power-package-and-method-of-fabricating-same-dt20080424ptan20080096319.php Wed, 30 Apr 2008 12:35:01 -0700 In one embodiment of the invention, a lead-frame is designed for use in IC packages such as those conforming to the TO 220 standard or other standards for power packages. The device areas of the lead-frame are arranged in columns, and each column is molded so as to expose a... http://www.freshpatents.com/High-density-chip-packages-methods-of-forming-and-systems-including-same-dt20080424ptan20080096320.php Wed, 30 Apr 2008 12:35:01 -0700 Methods and devices for multi-chip stacks are shown. A method is shown that assembles multiple chips into stacks by stacking wafers prior to dicing into individual chips. Methods shown provide removal of defective chips and their replacement during the assembly process to improve manufacturing yield.... http://www.freshpatents.com/Semiconductor-chip-package-manufacturing-method-and-structure-thereof-dt20080424ptan20080096321.php Wed, 30 Apr 2008 12:35:01 -0700 A semiconductor chip package manufacturing method and a structure thereof are provided. The manufacturing method includes: providing a base having an image sensor chip and an encapsulant, in which the image sensor chip has pads and an active area; placing a transparent insulator on the active area; forming an insulation... http://www.freshpatents.com/Manufacturing-method-of-semiconductor-chip-dt20080424ptan20080096322.php Wed, 30 Apr 2008 12:35:01 -0700 The present invention provides a method of manufacturing a semiconductor chip formed with an adhesive film at a back surface thereof, comprising the steps of applying a die bond material onto a dummy wafer by a spin coat method to form a coating film, bonding a back surface of a... http://www.freshpatents.com/Integrated-circuit-die-package-interconnect-dt20080424ptan20080096323.php Wed, 30 Apr 2008 12:35:01 -0700 A system may include a plurality of pliant conductive elements, a first end of one of the plurality of pliant conductive elements to be electrically coupled to a first electrical contact of an integrated circuit substrate and a second end of the one of the plurality of pliant conductive elements... http://www.freshpatents.com/Chip-packaging-process-dt20080424ptan20080096325.php Wed, 30 Apr 2008 12:35:01 -0700 A chip packaging process is provided. First, a cavity is formed on a heat sink. A first encapsulant is formed on the bottom of the cavity. A circuit substrate is disposed over the heat sink. The circuit substrate has an opening that corresponds in position to the cavity. Thereafter, a... http://www.freshpatents.com/Electronic-assemblies-having-a-low-processing-temperature-dt20080424ptan20080096324.php Wed, 30 Apr 2008 12:35:01 -0700 Embodiments relate to electronic assemblies and methods for forming electronic assemblies. One method includes providing a die and a copper heat spreader that are to be coupled to one another through a thermal interface material. A layer of tin is formed on the copper heat spreader. The heat spreader and... http://www.freshpatents.com/Method-for-making-advanced-smart-cards-with-integrated-electronics-using-isotropic-thermoset-adhesive-materials-with-high-quality-exterior-surfaces-dt20080424ptan20080096326.php Wed, 30 Apr 2008 12:35:01 -0700 Advanced Smart Cards and similar form factors (e.g. documents, tags) having high quality external surfaces of Polyvinylchloride (PVC), Polycarbonate (PC), synthetic paper or other suitable material can be made with highly sophisticated electronic components (e.g. Integrated Circuit chips, batteries, microprocessors, Light Emitting Diodes, Liquid Crystal Displays, polymer dome switches, and... http://www.freshpatents.com/Novel-monolithic-combo-nonvolatile-memory-allowing-byte-page-and-block-write-with-no-disturb-and-divided-well-in-the-cell-array-using-a-unified-cell-structure-and-technology-with-a-new-scheme-of-decoder-and-layout-dt20080424ptan20080096327.php Wed, 30 Apr 2008 12:35:01 -0700 A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo,... http://www.freshpatents.com/Nonvolatile-memory-devices-and-methods-of-forming-the-same-dt20080424ptan20080096328.php Wed, 30 Apr 2008 12:35:01 -0700 A memory device includes a substrate having a cell region, a low voltage region and a high voltage region. A ground selection transistor, a string selection transistor and a cell transistor are in the cell region, a low voltage transistor is in the low voltage region, and a high voltage... http://www.freshpatents.com/Method-of-manufacturing-thin-film-device-electro-optic-device-and-electronic-instrument-dt20080424ptan20080096329.php Wed, 30 Apr 2008 12:35:01 -0700 A method of manufacturing a thin film device includes: manufacturing a multi-layered structure in which a transfer layer including a thin film device is transferred to a first surface of the transfer-target substrate; and adhering a second surface of the transfer-target substrate, to which the transfer layer was transferred, to... http://www.freshpatents.com/High-performance-cmos-soi-devices-on-hybrid-crystal-oriented-substrates-dt20080424ptan20080096330.php Wed, 30 Apr 2008 12:35:01 -0700 An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing... http://www.freshpatents.com/Method-for-fabricating-high-compressive-stress-film-and-strained-silicon-transistors-dt20080424ptan20080096331.php Wed, 30 Apr 2008 12:35:01 -0700 A method for fabricating strained silicon transistors is disclosed. First, a semiconductor substrate is provided, in which the semiconductor substrate includes a gate, at least a spacer, and a source/drain region formed thereon. Next, a precursor, silane, and ammonia are injected, in which the precursor is reacted with silane and... http://www.freshpatents.com/Method-of-manufacturing-a-thin-film-transistor-substrate-dt20080424ptan20080096332.php Wed, 30 Apr 2008 12:35:01 -0700 A gate insulating layer, an active layer and a data metal film are sequentially formed on a substrate. A first photoresist pattern having a relatively small thickness in a channel forming area with respect to a thickness of the photoresist pattern not in the channel forming area is formed on... http://www.freshpatents.com/Method-of-manufacturing-a-thin-film-transistor-substrate-and-stripping-composition-dt20080424ptan20080096333.php Wed, 30 Apr 2008 12:35:01 -0700 A method of manufacturing a thin film transistor substrate includes forming a transistor thin layer pattern, forming a protecting layer, forming a photoresist film, forming a pixel electrode and a conductive layer that are separated from each other, stripping a photoresist pattern to remove the conductive layer using a stripping... http://www.freshpatents.com/Semiconductor-device-manufacturing-method-and-semiconductor-device-using-the-same-dt20080424ptan20080096334.php Wed, 30 Apr 2008 12:35:01 -0700 Including a process for forming a fin 12a having a first height and a fin 12b having a second height lower than the first height, a process for forming a silicon oxide film on the upper and side faces of each of the fins 12a and 12b, a process for... http://www.freshpatents.com/Sic-metal-semiconductor-field-effect-transistors-and-methods-for-producing-same-dt20080424ptan20080096335.php Wed, 30 Apr 2008 12:35:01 -0700 A silicon carbide metal semiconductor field-effect transistor includes a bi-layer silicon carbide buffer for improving electron confinement in the channel region and/or a layer disposed over at least the channel region of the transistor for suppressing surface effects caused by dangling bonds and interface states. Also, a sloped MESA fabrication... http://www.freshpatents.com/Method-of-forming-integrated-circuit-devices-having-n-mosfet-and-p-mosfet-transistors-with-elevated-and-silicided-source-drain-structures-dt20080424ptan20080096336.php Wed, 30 Apr 2008 12:35:01 -0700 An n-FET and a p-FET each have elevated source/drain structures. Optionally, the p-FET elevated-SOURCE/DRAIN structure is epitaxially grown from a p-FET recess formed in the substrate. Optionally, the n-FET elevated-SOURCE/DRAIN structure is epitaxially grown from an n-FET recess formed in the substrate. The n-FET and p-FET elevated-source/drain structures are both... http://www.freshpatents.com/Disposable-semiconductor-device-spacer-with-high-selectivity-to-oxide-dt20080424ptan20080096337.php Wed, 30 Apr 2008 12:35:01 -0700 The invention provides, in one aspect, a method of forming a semiconductor device. The method includes forming a gate dielectric layer and a gate electrode layer over a substrate. A portion of the gate dielectric layer and gate electrode layer is etched to form a plurality of gate electrodes. A... http://www.freshpatents.com/Methods-and-devices-employing-metal-layers-in-gates-to-introduce-channel-strain-dt20080424ptan20080096338.php Wed, 30 Apr 2008 12:35:01 -0700 A semiconductor device is fabricated having a metal stress inducing layer that facilitates channel mobility. A gate dielectric layer is formed over a semiconductor substrate. The metal stress inducing layer is formed over the gate dielectric layer. The metal stress inducing layer has a selected conductivity type and is formed... http://www.freshpatents.com/Cmos-devices-with-hybrid-channel-orientations-and-method-for-fabricating-the-same-dt20080424ptan20080096339.php Wed, 30 Apr 2008 12:35:01 -0700 The present invention relates to a method of fabricating a semiconductor substrate that includes forming at least first and second device regions, wherein the first device region includes a first recess having interior surfaces oriented along a first set of equivalent crystal planes, and wherein the second device region includes... http://www.freshpatents.com/Method-of-fabricating-a-nonvolatile-memory-device-dt20080424ptan20080096340.php Wed, 30 Apr 2008 12:35:01 -0700 A method of fabricating a nonvolatile memory device includes forming a charge tunneling layer on a semiconductor substrate, forming a charge trapping layer on the charge tunneling layer, forming a charge blocking layer on the charge trapping layer by supplying sequentially a metal source gas and an oxidizing gas onto... http://www.freshpatents.com/Method-for-manufacturing-a-resistor-random-access-memory-with-reduced-active-area-and-reduced-contact-areas-dt20080424ptan20080096341.php Wed, 30 Apr 2008 12:35:01 -0700 A method for manufacturing a memory device comprises patterning a dielectric layer and a conductive layer to align near the center of the top surface of a first contact drain plug and near the center of the top surface of a second contact drain plug. A first electrode is formed... http://www.freshpatents.com/Cmos-circuits-including-a-passive-element-having-a-low-end-resistance-dt20080424ptan20080096342.php Wed, 30 Apr 2008 12:35:01 -0700 The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits, as well as methods for forming such CMOS circuits. More specifically, the present invention relates to CMOS circuits that contain passive elements, such as buried resistors, capacitors, diodes, inductors, attenuators, power dividers, and antennas, etc., which are characterized by an end... http://www.freshpatents.com/Fabricating-method-of-cmos-dt20080424ptan20080096343.php Wed, 30 Apr 2008 12:35:01 -0700 A method of forming a metal-oxide-semiconductor (MOS) device is provided. The method includes the following steps. First, a conductive type MOS transistor is formed on a substrate. Then, a first etching stop layer is formed over the substrate to cover conformably the conductive type MOS transistor. Thereafter, a stress layer... http://www.freshpatents.com/Method-for-manufacturing-a-resistor-random-access-memory-with-a-self-aligned-air-gap-insulator-dt20080424ptan20080096344.php Wed, 30 Apr 2008 12:35:01 -0700 A method for manufacturing a resistor random access memory with a self-aligned air gap insulator. A high density plasma deposition on the stack of post-patterned layers produces a hard mask that is substantially near the center and overlying the cap layer of the stack of post-patterned layers. The high density... http://www.freshpatents.com/Nanoelectrochemical-cell-dt20080424ptan20080096345.php Wed, 30 Apr 2008 12:35:01 -0700 A method is provided for forming a NanoElectroChemical (NEC) cell. The method provides a bottom electrode with a top surface. Nanowire shells are formed. Each nanowire shell has a nanowire and a sleeve, with the nanowire connected to the bottom electrode top surface. A top electrode is formed overlying the... http://www.freshpatents.com/Method-for-preparing-a-trench-capacitor-structure-dt20080424ptan20080096346.php Wed, 30 Apr 2008 12:35:01 -0700 A method for preparing a trench capacitor structure first forms at least one trench in a substrate, and forms a capacitor structure in the bottom portion of the trench, wherein the capacitor structure includes a buried bottom electrode positioned on a lower outer surface of the trench, a first dielectric... http://www.freshpatents.com/Methods-of-forming-electronic-devices-including-electrodes-with-insulating-spacers-thereon-dt20080424ptan20080096347.php Wed, 30 Apr 2008 12:35:01 -0700 An electronic device may include a substrate, a conductive layer on the substrate, and an insulating spacer. The conductive electrode may have an electrode wall extending away from the substrate. The insulating spacer may be provided on the electrode wall with portions of the electrode wall being free of the... http://www.freshpatents.com/Contacts-for-semiconductor-devices-dt20080424ptan20080096348.php Wed, 30 Apr 2008 12:35:01 -0700 A memory device includes a number of memory cells and a dielectric layer formed over the memory cells. The memory device also includes contacts formed in the dielectric layer and spacers formed adjacent the side surfaces of the contacts. The spacers may inhibit leakage currents from the contacts.... http://www.freshpatents.com/Memory-device-and-method-of-manufacturing-the-same-dt20080424ptan20080096351.php Wed, 30 Apr 2008 12:35:01 -0700 A example embodiment may provide a memory device that may include an active pattern on a semiconductor substrate, a first charge trapping layer pattern on the active pattern, a first gate electrode on the first charge trapping layer pattern, a second charge trapping layer pattern on a sidewall of the... http://www.freshpatents.com/Method-of-fabricating-a-nonvolatile-memory-device-dt20080424ptan20080096349.php Wed, 30 Apr 2008 12:35:01 -0700 A method of fabricating a nonvolatile memory device includes forming a charge tunneling layer on a semiconductor substrate, forming a charge trapping layer on the charge tunneling layer, forming a first charge blocking layer on the charge trapping layer by supplying a metal source gas and a first oxidizing gas... http://www.freshpatents.com/Nonvolatile-memory-device-and-fabrication-method-dt20080424ptan20080096350.php Wed, 30 Apr 2008 12:35:01 -0700 Provided is a nonvolatile memory device and a fabrication method. The nonvolatile memory device includes an active region defined in a semiconductor substrate, a gate insulating layer formed on the active region and a plurality of gate patterns formed on the gate insulating layer, and crossing over the active region.... http://www.freshpatents.com/Method-of-forming-a-semiconductor-memory-device-and-semiconductor-memory-device-dt20080424ptan20080096352.php Wed, 30 Apr 2008 12:35:01 -0700 Gate stacks of an array of memory cells and a plurality of select transistors are formed above a carrier, the gate stacks being separated by spacers. An opening is formed between the spacers in an area that is provided for a source line. A sacrificial layer is applied to fill... http://www.freshpatents.com/Semiconductor-device-having-a-recessed-gate-and-asymmetric-dopant-regions-and-method-of-manufacturing-the-same-dt20080424ptan20080096353.php Wed, 30 Apr 2008 12:35:01 -0700 A semiconductor device, having a recessed gate and asymmetric dopant regions, comprises a semiconductor substrate having a trench with a first sidewall and a second sidewall, the heights of which are different from each other, a gate insulating layer pattern disposed on the semiconductor substrate, a gate stack disposed on... http://www.freshpatents.com/Vertical-mos-transistor-with-embedded-gate-and-its-fabrication-process-dt20080424ptan20080096354.php Wed, 30 Apr 2008 12:35:01 -0700 According to the invention, a transistor of vertical MOS type is produced in which an insulating assembly (28) formed above the drain (26) comprises insulating zones (42, 44) either side of the drain; cavities extend under the insulating assembly, either side of the channel (69); the gate (77a, 77b) is... http://www.freshpatents.com/Transistor-structure-of-memory-device-and-method-for-fabricating-the-same-dt20080424ptan20080096355.php Wed, 30 Apr 2008 12:35:01 -0700 A memory device includes an active area protruding from a semiconductor substrate. A recess is formed in the active area. A field oxide layer is formed on the semiconductor substrate. A gate electrode extends across the active area while being overlapped with the recess. A gate insulation layer is interposed... http://www.freshpatents.com/Substrate-having-silicon-germanium-material-and-stressed-silicon-nitride-layer-dt20080424ptan20080096356.php Wed, 30 Apr 2008 12:35:01 -0700 A method of fabricating a semiconductor device includes providing a region having doped silicon region on a substrate, and forming a silicon germanium material adjacent to the region on the substrate. A stressed silicon nitride layer is formed over at least a portion of the doped silicon region on the... http://www.freshpatents.com/Method-for-manufacturing-a-memory-device-dt20080424ptan20080096357.php Wed, 30 Apr 2008 12:35:01 -0700 A method for manufacturing a memory device that includes using a gap-filling material that inhibits charge coupling between memory devices. A semiconductor material is provided that has an active region and an isolation region. A charge trapping structure is formed over the active region and a layer of semiconductor material... http://www.freshpatents.com/Method-of-fabricating-semiconductor-device-having-reduced-contact-resistance-dt20080424ptan20080096358.php Wed, 30 Apr 2008 12:35:01 -0700 Provided is a method for fabricating a semiconductor device having reduced contact resistance. In the method, gate patterns defining a narrow opening and a wide opening are formed having an upper portion of a predetermined region of a semiconductor substrate. After gate spacers are formed on sidewalls of the gate... http://www.freshpatents.com/Method-of-determining-angle-misalignment-in-beam-line-ion-implanters-dt20080424ptan20080096359.php Wed, 30 Apr 2008 12:35:01 -0700 A method includes directing an ion beam at a plurality of differing incident angles with respect to a target surface of a substrate to implant ions into a plurality of portions of the substrate, wherein each one of the plurality of differing incident angles is associated with a different one... http://www.freshpatents.com/Semiconductor-wafer-suitable-for-forming-a-semiconductor-junction-diode-device-and-method-of-forming-same-dt20080424ptan20080096360.php Wed, 30 Apr 2008 12:35:01 -0700 A method is provided of making a semiconductor wafer for a semiconductor junction diode device having a target forward voltage drop and a target reverse breakdown voltage. The method begins by doping a semiconductor substrate of a first conductivity type through the back surface with a first dopant of the... http://www.freshpatents.com/Structure-for-realizing-integrated-circuit-having-schottky-diode-and-method-of-fabricating-the-same-dt20080424ptan20080096361.php Wed, 30 Apr 2008 12:35:01 -0700 An integrated circuit structure in which a plurality of Schottky diodes and a capacitor are integrally formed. The integrated circuit structure includes a substrate including an N-type semiconductor doped with N-type impurities and a P-type semiconductor doped with P-type impurities; a first conductive layer laminated on the substrate so that... http://www.freshpatents.com/Plasma-display-panel-and-manufacturing-method-of-the-same-dt20080424ptan20080096362.php Wed, 30 Apr 2008 12:35:01 -0700 A plasma display panel includes a sealing member that encloses a gas filled space, a first substrate and a second substrate that sandwich the gas filled space and the sealing member, a first insulator layer that is sandwiched between the first substrate and the sealing member, and a second insulator... http://www.freshpatents.com/High-dielectric-constant-materials-dt20080424ptan20080096363.php Wed, 30 Apr 2008 12:35:01 -0700 An integrated circuit can be formed with a high-k dielectric layer. A first titanium oxide layer is deposited over a substrate using a first ALD process. A first metal oxide layer is also deposited over the substrate using a second ALD process. A second titanium oxide layer is deposited over... http://www.freshpatents.com/Conformal-liner-for-gap-filling-dt20080424ptan20080096364.php Wed, 30 Apr 2008 12:35:01 -0700 Gap filling between features which are closely spaced is significantly improved by initially depositing a thin conformal layer followed by depositing a layer of gap filling dielectric material. Embodiments include depositing a thin conformal layer of silicon nitride or silicon oxide, as by atomic layer deposition or pulsed layer deposition,... http://www.freshpatents.com/Permanent-wafer-bonding-using-metal-alloy-preform-discs-dt20080424ptan20080096365.php Wed, 30 Apr 2008 12:35:01 -0700 A method for fabricating semiconductor devices at the wafer level, and devices fabricated using the method, are described. Wafer-level bonding using a relatively thick layer of electrically conducting bond medium was used to achieve void-free permanent wafer level bonding. The bond medium can be introduced to the pre-bonded wafers by... http://www.freshpatents.com/Method-for-forming-conductive-layer-and-substrate-having-the-same-and-method-for-manufacturing-semiconductor-device-dt20080424ptan20080096366.php Wed, 30 Apr 2008 12:35:01 -0700 A separation layer is formed over a substrate having a depressed portion, using a silane coupling agent; a conductive layer and an insulating layer that covers the conductive layer are formed in the depressed portion over the separation layer; and a sticky member is attached to the insulating layer, then... http://www.freshpatents.com/Method-for-laser-dicing-of-a-substrate-dt20080424ptan20080096367.php Wed, 30 Apr 2008 12:35:01 -0700 The invention relates to a method for dicing a substrate with a laser apparatus, comprising the steps of delivering a laser beam (15) from said laser apparatus to said substrate to dice said substrate (1) in at least two dies. A first assist gas is supplied at the substrate during... http://www.freshpatents.com/Wafer-processing-method-dt20080424ptan20080096368.php Wed, 30 Apr 2008 12:35:01 -0700 A water processing method for providing a gettering sink effect to a wafer having a plurality of streets which are formed in a lattice pattern on the front surface of a substrate and devices which are formed in a plurality of areas sectioned by the plurality of streets, comprising the... http://www.freshpatents.com/Apparatus-and-method-for-high-throughput-chemical-vapor-deposition-dt20080424ptan20080096369.php Wed, 30 Apr 2008 12:35:01 -0700 The invention relates to a device for depositing at least one especially thin layer onto at least one substrate (9). Said device comprises a process chamber (1, 20, 11, 11′, 40, 21), housed in a reactor housing (2) and comprising a movable susceptor (20) which carries the at least one... http://www.freshpatents.com/Method-of-manufacturing-dual-orientation-wafers-dt20080424ptan20080096370.php Wed, 30 Apr 2008 12:35:01 -0700 Disclosed is a method of manufacturing dual orientation wafers. A trench is formed in a multi-layer wafer to a silicon substrate with a first crystalline orientation. The trench is filled with a silicon material (e.g., amorphous silicon or polysilicon trench). Isolation structures are formed to isolate the silicon material in... http://www.freshpatents.com/Process-for-producing-p-doped-and-epitaxially-coated-semiconductor-wafers-from-silicon-dt20080424ptan20080096371.php Wed, 30 Apr 2008 12:35:01 -0700 The Czochralski method is used for producing p−-doped and epitaxially coated semiconductor wafers from silicon, wherein a silicon single crystal is pulled, and during the pulling is doped with boron, hydrogen and nitrogen, and the single crystal thus obtained is processed to form p−-doped semiconductor wafers which are epitaxially coated.... http://www.freshpatents.com/Patterning-of-doped-poly-silicon-gates-dt20080424ptan20080096372.php Wed, 30 Apr 2008 12:35:01 -0700 A method is provided for the patterning of a stack comprising elements that do not form volatile compounds during conventional reactive ion etching. More specifically the element(s) are Lanthanide elements such as Ytterbium (Yb) and the patterning preferably relates to the dry etching of silicon and/or germanium comprising structures (e.g.... http://www.freshpatents.com/Fabrication-of-ccd-image-sensors-using-single-layer-polysilicon-dt20080424ptan20080096373.php Wed, 30 Apr 2008 12:35:01 -0700 A method for fabricating CCD imaging structures having single layer polysilicon gates and employing conventional photolithographic techniques and equipment is disclosed. The comprises the steps of providing a silicon substrate; growing a dielectric layer substantially overlying the silicon substrate; depositing a first layer of polysilicon substantially overlaying the dielectric layer;... http://www.freshpatents.com/Selective-removal-of-rare-earth-based-high-k-materials-in-a-semiconductor-device-dt20080424ptan20080096374.php Wed, 30 Apr 2008 12:35:01 -0700 A method is disclosed for the selective removal of rare earth based high-k materials such as rare earth scandate high-k materials (e.g. DyScO3) over silicon or silicon dioxide. As an example Dy and Sc comprising high-k materials are used as a high-k material in gate stacks of a semiconductor device.... http://www.freshpatents.com/Contact-structure-and-method-of-forming-the-same-dt20080424ptan20080096378.php Wed, 30 Apr 2008 12:35:01 -0700 In a method of forming a contact structure, first and second conductive structures may be formed on a lower structure to be spaced from each other. An insulating layer may be formed on the lower structure to cover the first and second conductive structures. A first hole exposing the first... http://www.freshpatents.com/Method-for-making-memory-cell-device-dt20080424ptan20080096375.php Wed, 30 Apr 2008 12:35:01 -0700 A memory cell device, including a memory material element switchable between electrical property states by the application of energy, includes depositing an electrical conductor layer, depositing dielectric material layers and etching to create a first electrode and voids. A memory material is applied into a void to create a memory... http://www.freshpatents.com/Semiconductor-device-and-method-for-forming-the-same-dt20080424ptan20080096377.php Wed, 30 Apr 2008 12:35:01 -0700 In one embodiment a semiconductor device includes odd contacts and respective odd lines. Spacers are formed on sidewalls of the odd lines and even openings for even lines are formed by performing an etching process. Even contacts are formed in the even openings and then even lines are formed.... http://www.freshpatents.com/Transparent-zinc-oxide-electrode-having-a-graded-oxygen-content-dt20080424ptan20080096376.php Wed, 30 Apr 2008 12:35:01 -0700 A method of reactively sputtering from a metallic zinc target a transparent conductive oxide electrode of zinc oxide from a metallic zine in a silicon photo diode device and the resultant product, such as a solar cell. The electrode in deposited on a transparent substrate in at least two steps.... http://www.freshpatents.com/Flip-chip-metallization-method-and-devices-dt20080424ptan20080096379.php Wed, 30 Apr 2008 12:35:01 -0700 Interconnect metallization schemes and devices for flip chip bonding are disclosed and described. Metallization schemes include an adhesion layer, a diffusion barrier layer, a wettable layer, and a wetting stop layer. Various thicknesses and materials for use in the different layers are disclosed and are particularly useful for metallization in... http://www.freshpatents.com/Low-k-interconnect-structures-with-reduced-rc-delay-dt20080424ptan20080096380.php Wed, 30 Apr 2008 12:35:01 -0700 A method for forming an integrated circuit includes forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, forming a dielectric barrier layer covering at least sidewalls of the opening, performing a treatment to improve a wetting ability of the dielectric barrier... http://www.freshpatents.com/Atomic-layer-deposition-process-for-iridium-barrier-layers-dt20080424ptan20080096381.php Wed, 30 Apr 2008 12:35:01 -0700 An iridium barrier and adhesion layer for use with copper interconnects within integrated circuits is formed using an atomic layer deposition (ALD) process. The ALD process uses an organometallic iridium precursor and at least one co-reactant.... http://www.freshpatents.com/Method-for-producing-an-integrated-circuit-including-a-connection-contact-on-a-semiconductor-body-dt20080424ptan20080096382.php Wed, 30 Apr 2008 12:35:01 -0700 A method for producing an integrated circuit is disclosed. One embodiment includes application of a barrier layer on the surface of the semiconductor body and in the trench, which barrier layer completely fills the trench and is at least partly deposited by using a CVD method. A metallization layer is... http://www.freshpatents.com/Method-of-manufacturing-a-semiconductor-device-with-multiple-dielectrics-dt20080424ptan20080096383.php Wed, 30 Apr 2008 12:35:01 -0700 A method of manufacturing a semiconductor device with at least a first dielectric material and a second dielectric material is disclosed. In one aspect, the method comprises providing a first dielectric material on a substrate. The method further comprises providing a patterned sacrificial layer covering the first dielectric material in... http://www.freshpatents.com/Method-of-forming-damascene-filament-wires-dt20080424ptan20080096384.php Wed, 30 Apr 2008 12:35:01 -0700 A method of forming a semiconductor device. A first dielectric layer is deposited on and in direct mechanical contact with the substrate. A first hard mask is deposited on the first dielectric layer. A first and second trench is formed within the first dielectric layer and the first hard mask.... http://www.freshpatents.com/Slurry-composition-for-forming-tungsten-pattern-and-method-for-manufacturing-semiconductor-device-using-the-same-dt20080424ptan20080096385.php Wed, 30 Apr 2008 12:35:01 -0700 A method for manufacturing a semiconductor device with a slurry composition for forming a tungsten pattern. The method comprises: forming a trench in an insulating film formed on a substrate; depositing a tungsten film over the insulating film including the trench; first polishing a tungsten film with a first slurry... http://www.freshpatents.com/Method-of-forming-a-phase-changeable-layer-and-method-of-manufacturing-a-semiconductor-memory-device-using-the-same-dt20080424ptan20080096386.php Wed, 30 Apr 2008 12:35:01 -0700 A phase-changeable layer and a method of forming the same are disclosed. In the method, a first hydrogen gas is introduced into a reaction chamber into which a substrate is loaded at a first flow rate to form first plasma. A primary cyclic CVD process is carried out using precursors... http://www.freshpatents.com/Method-for-removing-photoresist-layer-and-method-of-forming-opening-dt20080424ptan20080096387.php Wed, 30 Apr 2008 12:35:01 -0700 A method for removing a photoresist layer is provided. The method is suitable for a dielectric layer, wherein the dielectric layer has a patterned photoresist layer formed thereon and a metal silicide layer disposed thereunder and there is an etching stop layer disposed between the dielectric layer and the metal... http://www.freshpatents.com/Planarization-method-using-hybrid-oxide-and-polysilicon-cmp-dt20080424ptan20080096388.php Wed, 30 Apr 2008 12:35:01 -0700 A method of planarizing a semiconductor device is provided. The semiconductor device includes a substrate, first and second components provided on the surface of the substrate, and a first material provided between and above the first and second components. The first component has a height greater than a height of... http://www.freshpatents.com/Copper-damascene-chemical-mechanical-polishing--cmp--for-thin-film-head-writer-fabrication-dt20080424ptan20080096389.php Wed, 30 Apr 2008 12:35:01 -0700 In one method and embodiment of the present invention, at least one coil layer is formed in a write head, using a two-slurry step of copper damascene chemical mechanical polishing method with a first slurry step removing the undesirable copper that is on top of the tantalum barrier layer and... http://www.freshpatents.com/Halide-anions-for-metal-removal-rate-control-dt20080424ptan20080096390.php Wed, 30 Apr 2008 12:35:01 -0700 The inventive chemical-mechanical polishing composition comprises a liquid carrier, hydrogen peroxide, benzotriazole, and a halogen anion. The inventive method comprises chemically-mechanically polishing a substrate with the polishing composition.... http://www.freshpatents.com/Method-of-fabricating-semiconductor-device-having-fine-contact-holes-dt20080424ptan20080096391.php Wed, 30 Apr 2008 12:35:01 -0700 A method for fabricating a semiconductor device having fine contact holes is exemplary disclosed. The method includes forming an isolation layer defining active regions on a semiconductor substrate. An interlayer dielectric layer is formed on the semiconductor substrate having the isolation layer. First molding patterns are formed on the interlayer... http://www.freshpatents.com/Ashing-system-dt20080424ptan20080096392.php Wed, 30 Apr 2008 12:35:01 -0700 An ashing system capable of restraining etching and damage of an oxide film or a nitride film on a semiconductor substrate and ashing a resist uniformly at a very high rate is to be provided. The ashing system includes a reaction tube, a coil and a high frequency power source... http://www.freshpatents.com/Apparatus-and-method-of-etching-a-semiconductor-substrate-dt20080424ptan20080096393.php Wed, 30 Apr 2008 12:35:01 -0700 An apparatus for etching a semiconductor substrate may include a bath, a reaction preventing layer, and a nozzle. The bath may receive a chemical solution. Grooves may be formed at the inner wall of the bath. The reaction preventing layer may be formed on the inner wall and in the... http://www.freshpatents.com/Gate-dielectric-layers-and-methods-of-fabricating-gate-dielectric-layers-dt20080424ptan20080096394.php Wed, 30 Apr 2008 12:35:01 -0700 A method of forming a gate dielectric layer includes forming a gate dielectric layer over a substrate. The gate dielectric layer is processed with carbon-containing ions. The gate dielectric layer is thermally processed, thereby providing the gate dielectric layer with a level of carbon between about 1 atomic % and... http://www.freshpatents.com/Producing-method-of-semiconductor-device-dt20080424ptan20080096395.php Wed, 30 Apr 2008 12:35:01 -0700 Disclosed is a producing method of a semiconductor device comprising: film thinning a silicon oxide film by heating the silicon oxide film formed after a surface of a silicon substrate is etched by chemical liquid, and one of thermal oxidizing by heating the thinned silicon oxide film to oxidize the... http://www.freshpatents.com/Methods-of-forming-low-hydrogen-concentration-charge-trapping-layer-structures-for-non-volatile-memory-dt20080424ptan20080096396.php Wed, 30 Apr 2008 12:35:01 -0700 Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping...