http://www.freshpatents.com/Static-information-storage-and-retrieval-dtnewntc365.php USPTO Class 365 - Static information storage and retrieval en-us Mon, 20 May 2013 13:38:35 -0700 1000 Wednesday Thursday Friday Saturday Sunday 141 31 http://www.freshpatents.com/index.php?rss=true http://www.freshpatents.com/images/freshpatentsnav_rss.gif http://www.freshpatents.com/-dt20130516ptan20130121053.php Mon, 20 May 2013 13:38:35 -0700 A content addressable memory (CAM) device can include a number of bit lines. One or more of the bit lines can be connected to storage circuits of CAM cells in a corresponding column. Each CAM cell can include compare circuits that compare a stored value one or more compare data... http://www.freshpatents.com/-dt20130516ptan20130121054.php Mon, 20 May 2013 13:38:35 -0700 A three-dimensional integrated circuit comprising a submicroscale integrated-circuit substrate and n nanoscale layers stacked above the submicroscale integrated-circuit substrate, a nanowire-junction memory element in each of which is independently controlled by two submicroscale subcomponents within the submicroscale integrated-circuit substrate, the first submicroscale subcomponent coupled through a first set of switches... http://www.freshpatents.com/-dt20130516ptan20130121055.php Mon, 20 May 2013 13:38:35 -0700 A word line driver cell suitable for RAM devices such as SRAM, static random access memory devices, is provided. The word line driver cell is compatible with double pattern processing techniques and enables the formation of all word lines from a single metal layer which, in turn, enables overlying and... http://www.freshpatents.com/-dt20130516ptan20130121056.php Mon, 20 May 2013 13:38:35 -0700 The present disclosure includes methods and apparatuses that include resistive memory. A number of embodiments include a first memory cell coupled to a data line and including a first resistive storage element and a first access device, a second memory cell coupled to the data line and including a second... http://www.freshpatents.com/-dt20130516ptan20130121058.php Mon, 20 May 2013 13:38:35 -0700 A circuit and a method for controlling the write timing of a non-volatile memory are provided. The method includes the following steps. First, a resistance state switching of at least one memory cell of the non-volatile memory executing a writing operation is monitored to output a control signal. The memory... http://www.freshpatents.com/-dt20130516ptan20130121063.php Mon, 20 May 2013 13:38:35 -0700 A memory device that can prevent degradation in characteristics of a diode and the destruction due to the miniaturization includes: a substrate; first electrodes, a second electrode, and a third electrode that are stacked above the substrate; a variable resistance layer between the first and second electrodes; and a non-conductive... http://www.freshpatents.com/-dt20130516ptan20130121059.php Mon, 20 May 2013 13:38:35 -0700 A multi-valued logic device having an improved reliability includes a conversion unit configured to convert a multi level signal into a plurality of partial signals; and a plurality of nonvolatile memory devices configured to individually store the plurality of partial signals, wherein a number of bits of each of the... http://www.freshpatents.com/-dt20130516ptan20130121060.php Mon, 20 May 2013 13:38:35 -0700 Non-volatile memory elements, memory devices including the same, and methods for operating and manufacturing the same may include a memory layer between a first electrode and a second electrode spaced apart from the first electrode. The memory layer may include a first material layer and a second material layer, and... http://www.freshpatents.com/-dt20130516ptan20130121061.php Mon, 20 May 2013 13:38:35 -0700 A method is provided for programming a memory cell in a memory array. The memory cell includes a resistivity-switching layer of a metal oxide or nitride compound, and the metal oxide or nitride compound includes exactly one metal. The method includes programming the memory cell by changing the resistivity-switching layer... http://www.freshpatents.com/-dt20130516ptan20130121057.php Mon, 20 May 2013 13:38:35 -0700 An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has two adjustable resistors and two heating elements. A dielectric material separates the heating elements from the adjustable resistors. One heating element alters the resistance of one... http://www.freshpatents.com/-dt20130516ptan20130121062.php Mon, 20 May 2013 13:38:35 -0700 A method for rewriting a memory array (408) with a number of memory elements (206) includes performing a rewrite process to change the memory array (408) from an initial state to a target state in a manner that avoids violating to a set of weight constraints at any time during... http://www.freshpatents.com/-dt20130516ptan20130121064.php Mon, 20 May 2013 13:38:35 -0700 The invention contained herein provides electrical circuits and driving methods to operate a memory cell comprising a capacitance coupled to a breakover conduction switch such as a thyristor, DIAC or one or more complementary transistor pairs. The memory cell comprises a cell capacitance for storing a memory state and for... http://www.freshpatents.com/-dt20130516ptan20130121065.php Mon, 20 May 2013 13:38:35 -0700 A dynamic wordline assist circuit for improving performance of an SRAM. An SRAM is disclosed that includes a plurality of memory cells, wherein each memory cell is coupled to a wordline and a pair of bitlines; and a wordline assist circuit coupled to the wordline, wherein the wordline assist circuit... http://www.freshpatents.com/-dt20130516ptan20130121066.php Mon, 20 May 2013 13:38:35 -0700 A method of establishing a reference level includes providing first and second non-overlapping paths from a first node to a second node, providing first and second reference magnetic random access memory (MRAM) elements in the first path, providing third and fourth reference MRAM elements in the second path, measuring a... http://www.freshpatents.com/-dt20130516ptan20130121067.php Mon, 20 May 2013 13:38:35 -0700 A high speed, low power method to control and switch the magnetization direction and/or helicity of a magnetic region in a magnetic device for memory cells using spin polarized electrical current. The magnetic device comprises a reference magnetic layer with a fixed magnetic helicity and/or magnetization direction and a free... http://www.freshpatents.com/-dt20130516ptan20130121068.php Mon, 20 May 2013 13:38:35 -0700 The disclosed subject matter relates to a non-volatile memory bit cell (500 or 600) for solid-state data storage, including, e.g., an elongated magnetic element (102) or “dot”. For appropriate geometry and dimensions of the dot, a two-fold, energetically-degenerate micromagnetic configuration (100 or 200) can be stabilized. Such a stable configuration... http://www.freshpatents.com/-dt20130516ptan20130121069.php Mon, 20 May 2013 13:38:35 -0700 An internal voltage generating circuit includes a divided voltage generator configured to generate a divided voltage by dividing a feedback internal voltage level at a division ratio corresponding to an operation mode control signal, a voltage detector configured to detect a level of the divided voltage based on a reference... http://www.freshpatents.com/-dt20130516ptan20130121070.php Mon, 20 May 2013 13:38:35 -0700 A memory device includes first and second inverters cross-coupled between first and second nodes. The first inverter is configured to be supplied by a first supply voltage via a first transistor and the second inverter is configured to be supplied by the first supply voltage via a second transistor. A... http://www.freshpatents.com/-dt20130516ptan20130121071.php Mon, 20 May 2013 13:38:35 -0700 The programming disturb effects in a semiconductor non-volatile memory device can be mitigated by biasing unselected memory cells with a negative voltage while a well containing the memory cells receives a positive voltage. A selected memory cell in the well can be biased with a negative voltage while the well... http://www.freshpatents.com/-dt20130516ptan20130121072.php Mon, 20 May 2013 13:38:35 -0700 Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of... http://www.freshpatents.com/-dt20130516ptan20130121073.php Mon, 20 May 2013 13:38:35 -0700 According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On... http://www.freshpatents.com/-dt20130516ptan20130121074.php Mon, 20 May 2013 13:38:35 -0700 According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On... http://www.freshpatents.com/-dt20130516ptan20130121075.php Mon, 20 May 2013 13:38:35 -0700 A non-volatile memory system that has multiple memory banks initially assigns logical addresses to memory banks according to an assignment scheme, maintains this assignment for a period of time, then identifies frequently-written data (“hot-data”) assigned to a memory bank that is heavily worn over that period of time and reassigns... http://www.freshpatents.com/-dt20130516ptan20130121076.php Mon, 20 May 2013 13:38:35 -0700 A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not... http://www.freshpatents.com/-dt20130516ptan20130121077.php Mon, 20 May 2013 13:38:35 -0700 In a three dimensional stacked nonvolatile semiconductor memory according to the present invention, a first block has a selected first cell unit including a memory cell to be read and a non-selected second cell unit not including a memory cell to be read. A read potential or a transfer potential... http://www.freshpatents.com/-dt20130516ptan20130121078.php Mon, 20 May 2013 13:38:35 -0700 A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which... http://www.freshpatents.com/-dt20130516ptan20130121079.php Mon, 20 May 2013 13:38:35 -0700 The present invention provides a NOR flash memory cell. The NOR flash memory cell includes a first transistor, a second transistor and at least one third transistor. The first transistor has a control terminal, a first terminal and a second terminal. The control terminal used to receive a word line... http://www.freshpatents.com/-dt20130516ptan20130121080.php Mon, 20 May 2013 13:38:35 -0700 A method for operating a memory (28) that includes a plurality of analog memory cells (32) includes storing data in the memory by writing first storage values to the cells. Second storage values are read from the cells, and a Cumulative Distribution Function (CDF) of the second storage values is... http://www.freshpatents.com/-dt20130516ptan20130121081.php Mon, 20 May 2013 13:38:35 -0700 A nonvolatile semiconductor memory device includes a memory unit and a control unit. The memory unit includes a multilayer structure including electrode films and inter-electrode insulating films alternately stacked in a first direction; a semiconductor pillar piercing the multilayer structure in the first direction; a memory layer provided between the... http://www.freshpatents.com/-dt20130516ptan20130121082.php Mon, 20 May 2013 13:38:35 -0700 A method of operating a nonvolatile memory device includes determining whether a program operation is performed on even memory cells coupled to even bit lines of a selected page, setting a coupling resistance value between odd bit lines of the selected page and page buffers depending on whether the program... http://www.freshpatents.com/-dt20130516ptan20130121083.php Mon, 20 May 2013 13:38:35 -0700 In one embodiment, the method includes detecting a noise level of a common source line, and adjusting a frequency of program-verify operations on a memory cell during a programming loop based on the detected noise level.... http://www.freshpatents.com/-dt20130516ptan20130121084.php Mon, 20 May 2013 13:38:35 -0700 A method includes providing data including hard bit data and soft bit data to a rank modulation decoder.... http://www.freshpatents.com/-dt20130516ptan20130121085.php Mon, 20 May 2013 13:38:35 -0700 A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the first region, a control gate disposed over the channel region and laterally adjacent to the floating gate... http://www.freshpatents.com/-dt20130516ptan20130121086.php Mon, 20 May 2013 13:38:35 -0700 A memory includes at least first and second banks of single-port memory elements, a first local controller adapted to send read and write instructions to the first memory bank, and a second local controller adapted to send read and write instructions to the second memory bank. A global controller is... http://www.freshpatents.com/-dt20130516ptan20130121088.php Mon, 20 May 2013 13:38:35 -0700 A memory including a boost circuit configured to supply a voltage higher than a supply voltage to a word line. The boost circuit includes a first capacitor having a first capacitor dielectric thickness. The boost circuit further includes a transmission gate coupled to the word line and the first capacitor,... http://www.freshpatents.com/-dt20130516ptan20130121087.php Mon, 20 May 2013 13:38:35 -0700 A memory bit cell includes a latch, a write port coupled to the latch, and a read port coupled to the latch. The write port includes a first set of devices having a first threshold voltage and a second set of devices having a second threshold voltage that is greater... http://www.freshpatents.com/-dt20130516ptan20130121089.php Mon, 20 May 2013 13:38:35 -0700 In accordance with an embodiment of the disclosure, systems and methods are provided for reducing an amount of peak power consumption in a device. In certain implementations, a first signal and a second signal are received, wherein the first signal and the second signal are indicative of amounts of power... http://www.freshpatents.com/-dt20130516ptan20130121090.php Mon, 20 May 2013 13:38:35 -0700 A semiconductor memory device includes memory cells arranged at regions where word lines and bit lines cross each other; a randomizing and de-randomizing circuit configured to perform a first randomizing operation on data to be programmed to the memory cells, based on a seed value, so as to generate first... http://www.freshpatents.com/-dt20130516ptan20130121091.php Mon, 20 May 2013 13:38:35 -0700 According to the system of the present invention, data (DQ) signals are outputted/received between a controller 100 and a memory 200 based on a data strobe signal sent out from the controller 100. The data strobe signal is independently and completely separated from a clock signal. The data strobe signal... http://www.freshpatents.com/-dt20130516ptan20130121093.php Mon, 20 May 2013 13:38:35 -0700 A memory access control device including: a bit position information storage unit storing bit position information indicating one or more bit positions in a bit sequence of a predetermined length; a reading unit configured to attempt to read a bit sequence from the range specified by the logical address received... http://www.freshpatents.com/-dt20130516ptan20130121092.php Mon, 20 May 2013 13:38:35 -0700 Disclosed herein is a device that includes a first semiconductor chip outputting a read command and a clock signal, a plurality of second semiconductor chips stacked to the first semiconductor chip, and a signal path electrically connected between the first and second semiconductor chips. Each of the second semiconductor chips... http://www.freshpatents.com/-dt20130516ptan20130121096.php Mon, 20 May 2013 13:38:35 -0700 A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal for delivering the clock driving signal to... http://www.freshpatents.com/-dt20130516ptan20130121094.php Mon, 20 May 2013 13:38:35 -0700 Embodiments of an integrated circuit (IC) comprising a delay-locked loop (DLL) are described. Some embodiments include first circuitry to generate a first clock signal by delaying an input clock signal by a first delay, second circuitry to determine a code based on the input clock signal and the first clock... http://www.freshpatents.com/-dt20130516ptan20130121095.php Mon, 20 May 2013 13:38:35 -0700 A DRAM coupled to a system LSI, the DRAM receiving a test pattern from the system LSI to store the test pattern, if a power source of the system LSI is turned on, outputting the stored test pattern to the system LSI, receiving a delay set value from the system... http://www.freshpatents.com/-dt20130516ptan20130121097.php Mon, 20 May 2013 13:38:35 -0700 A semiconductor memory device includes a signal generation unit configured to generate a toggling signal and first and second pulse signals in response to a test signal and a burst pulse signal. An address output unit may be configured to receive first to fourth input addresses and output sequentially first... http://www.freshpatents.com/-dt20130516ptan20130121098.php Mon, 20 May 2013 13:38:35 -0700 A serial memory may have memory arranged in a plurality of memory blocks, a serial interface for receiving a read instruction and associated memory address; and a controller configured to only store a plurality of most significant bits from each memory block which are accessed in parallel before an entire... http://www.freshpatents.com/-dt20130516ptan20130121099.php Mon, 20 May 2013 13:38:35 -0700 An amplifier circuit includes an amplification unit and a back-bias voltage providing unit. The amplification unit amplifies input data. The back-bias voltage providing unit provides selectively back-bias voltages of different levels to the amplification unit in an initial operation period of the amplification unit and a period after the initial... http://www.freshpatents.com/-dt20130516ptan20130121100.php Mon, 20 May 2013 13:38:35 -0700 A device and method to perform memory operations at a clock domain crossing is disclosed. In a particular embodiment, a method includes providing a first clock signal to a write clock input of a memory to write data to the memory. The data is read from the memory according to...